FROMLIST: dts/arm/st/f1: Add support for F103xG
Add a dtsi file for the F103xG chips, which have 1 MB of flash,
96 KB of ram, and several extra peripherals including ADC3 and
TIM9/10/11/12/13/14.
BUG=b:168351243
TEST=build chameleon
Change-Id: I93f0c4fd924a02740741e654476bea2a134ebfa9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/2412671
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: Paul Fagerburg <pfagerburg@chromium.org>
diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi
index 4711bed..548cd5e 100644
--- a/dts/arm/st/f1/stm32f103Xe.dtsi
+++ b/dts/arm/st/f1/stm32f103Xe.dtsi
@@ -45,6 +45,8 @@
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+ interrupts = <50 0>;
+ interrupt-names = "global";
status = "disabled";
label = "TIMERS_5";
@@ -53,7 +55,7 @@
status = "disabled";
st,prescaler = <0>;
label = "PWM_5";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
@@ -61,6 +63,8 @@
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+ interrupts = <54 0>;
+ interrupt-names = "global";
status = "disabled";
label = "TIMERS_6";
@@ -69,7 +73,7 @@
status = "disabled";
st,prescaler = <10000>;
label = "PWM_6";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
@@ -77,6 +81,8 @@
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+ interrupts = <55 0>;
+ interrupt-names = "global";
status = "disabled";
label = "TIMERS_7";
@@ -85,7 +91,7 @@
status = "disabled";
st,prescaler = <10000>;
label = "PWM_7";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
@@ -122,10 +128,33 @@
};
};
+ adc2: adc@40012800 {
+ compatible = "st,stm32-adc";
+ reg = <0x40012800 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+ /* Shares vector with ADC1 */
+ interrupts = <18 0>;
+ status = "disabled";
+ label = "ADC_2";
+ #io-channel-cells = <1>;
+ };
+
+ adc3: adc@40013c00 {
+ compatible = "st,stm32-adc";
+ reg = <0x40013c00 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
+ interrupts = <47 0>;
+ status = "disabled";
+ label = "ADC_3";
+ #io-channel-cells = <1>;
+ };
+
timers8: timers@40013400 {
compatible = "st,stm32-timers";
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+ interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+ interrupt-names = "brk", "up", "trgcom", "cc";
status = "disabled";
label = "TIMERS_8";
@@ -134,7 +163,7 @@
status = "disabled";
st,prescaler = <10000>;
label = "PWM_8";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
diff --git a/dts/arm/st/f1/stm32f103Xg.dtsi b/dts/arm/st/f1/stm32f103Xg.dtsi
new file mode 100644
index 0000000..60f4c1a
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103Xg.dtsi
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2020 Google, LLC
+ *
+ * SoC device tree include for STM32F103xG SoCs
+ * where 'x' is replaced for specific SoCs like {R,V,Z}
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f103Xe.dtsi>
+
+/ {
+ sram0: memory@20000000 {
+ reg = <0x20000000 DT_SIZE_K(96)>;
+ };
+
+ soc {
+ flash-controller@40022000 {
+ flash0: flash@8000000 {
+ /* Note that there are actually two banks of
+ * flash (512KB each) and two flash controllers.
+ * This matters if you're doing in-application
+ * flash programming and you need the
+ * read-while-write capabilities, but is
+ * otherwise a non-issue.
+ */
+ reg = <0x08000000 DT_SIZE_K(1024)>;
+ erase-block-size = <DT_SIZE_K(2)>;
+ };
+ };
+
+ timers9: timers@40014c00 {
+ compatible = "st,stm32-timers";
+ reg = <0x40014c00 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+ /* Shared with TIM1_BRK */
+ interrupts = <24 0>;
+ status = "disabled";
+ label = "TIMERS_9";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ st,prescaler = <10000>;
+ label = "PWM_9";
+ #pwm-cells = <3>;
+ };
+ };
+
+ timers10: timers@40015000 {
+ compatible = "st,stm32-timers";
+ reg = <0x40015000 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+ /* Shared with TIM1_UP */
+ interrupts = <25 0>;
+ status = "disabled";
+ label = "TIMERS_10";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ st,prescaler = <10000>;
+ label = "PWM_10";
+ #pwm-cells = <3>;
+ };
+ };
+
+ timers11: timers@40015400 {
+ compatible = "st,stm32-timers";
+ reg = <0x40015400 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+ /* Shared with TIM1_TRG_COM */
+ interrupts = <26 0>;
+ status = "disabled";
+ label = "TIMERS_11";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ st,prescaler = <10000>;
+ label = "PWM_11";
+ #pwm-cells = <3>;
+ };
+ };
+
+ timers12: timers@40001800 {
+ compatible = "st,stm32-timers";
+ reg = <0x40001800 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+ /* Shared with TIM8_BRK */
+ interrupts = <43 0>;
+ status = "disabled";
+ label = "TIMERS_12";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ st,prescaler = <10000>;
+ label = "PWM_12";
+ #pwm-cells = <3>;
+ };
+ };
+
+ timers13: timers@40001c00 {
+ compatible = "st,stm32-timers";
+ reg = <0x40001c00 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+ /* Shared with TIM8_UP */
+ interrupts = <44 0>;
+ status = "disabled";
+ label = "TIMERS_13";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ st,prescaler = <10000>;
+ label = "PWM_13";
+ #pwm-cells = <3>;
+ };
+ };
+
+ timers14: timers@40002000 {
+ compatible = "st,stm32-timers";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+ /* Shared with TIM8_TRG_COM */
+ interrupts = <45 0>;
+ status = "disabled";
+ label = "TIMERS_14";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ status = "disabled";
+ st,prescaler = <10000>;
+ label = "PWM_14";
+ #pwm-cells = <3>;
+ };
+ };
+
+ };
+};