commit | b46d76f4c4391c065616f14bb67f57542121a3e5 | [log] [tgz] |
---|---|---|
author | Tudor Timi <tudortimi@users.noreply.github.com> | Sat Oct 22 22:46:15 2022 +0300 |
committer | Tudor Timi <tudortimi@users.noreply.github.com> | Tue Nov 01 20:39:11 2022 +0200 |
tree | dd9b26571570fbe03a475f71b8d7e3d57514bd58 | |
parent | 3d7822b543fcbe0a94bcb345aa51169eb15372d8 [diff] |
Use dummy type as default for type parameters that should be passed by macro This causes a compile error for the test which doesn't specify the type, because we haven't implemented type inference yet.
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.
NOTE: for instructions on how to get going with SVUnit, go to www.agilesoc.com/svunit.
NOTE: Refer also to the FAQ at: www.agilesoc.com/svunit/svunit-FAQ
Go here for release notes.
SVUNIT_INSTALL
and PATH
environment variablesexport SVUNIT_INSTALL=`pwd` export PATH=$PATH:$SVUNIT_INSTALL"/bin"
You can source Setup.bsh
if you use the bash shell.
source Setup.bsh
You can source Setup.csh
if you use the csh shell.
source Setup.csh
SVUNIT_INSTALL
(i.e. where you are right now)Start a class-under-test:
// file: bogus.sv class bogus; endclass
create_unit_test.pl bogus.sv
// file: bogus_unit_test.sv `SVUNIT_TESTS_BEGIN //=================================== // Unit test: test_mytest //=================================== `SVTEST(test_mytest) `SVTEST_END `SVUNIT_TESTS_END
runSVUnit -s <simulator> # simulator is ius, questa, modelsim, riviera or vcs