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Gerd Hoffmanne4337852012-10-30 15:08:37 +01001/*
2 * QEMU USB EHCI Emulation
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or(at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "hw/usb/hcd-ehci.h"
Gerd Hoffmanne4337852012-10-30 15:08:37 +010019
20static const VMStateDescription vmstate_ehci_sysbus = {
21 .name = "ehci-sysbus",
22 .version_id = 2,
23 .minimum_version_id = 1,
Juan Quintela6e3d6522014-04-16 13:31:26 +020024 .fields = (VMStateField[]) {
Gerd Hoffmanne4337852012-10-30 15:08:37 +010025 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
26 VMSTATE_END_OF_LIST()
27 }
28};
29
30static Property ehci_sysbus_properties[] = {
31 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
32 DEFINE_PROP_END_OF_LIST(),
33};
34
Andreas Färber08f4c902013-06-06 15:41:09 +020035static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
Gerd Hoffmanne4337852012-10-30 15:08:37 +010036{
Andreas Färber08f4c902013-06-06 15:41:09 +020037 SysBusDevice *d = SYS_BUS_DEVICE(dev);
Andreas Färber5aa3ca92012-12-16 04:49:43 +010038 EHCISysBusState *i = SYS_BUS_EHCI(dev);
Andreas Färberd4614cc2013-06-06 15:41:10 +020039 EHCIState *s = &i->ehci;
40
41 usb_ehci_realize(s, dev, errp);
42 sysbus_init_irq(d, &s->irq);
43}
44
Gonglei4e289b12015-03-18 17:33:47 +080045static void usb_ehci_sysbus_reset(DeviceState *dev)
46{
47 SysBusDevice *d = SYS_BUS_DEVICE(dev);
48 EHCISysBusState *i = SYS_BUS_EHCI(d);
49 EHCIState *s = &i->ehci;
50
51 ehci_reset(s);
52}
53
Andreas Färberd4614cc2013-06-06 15:41:10 +020054static void ehci_sysbus_init(Object *obj)
55{
56 SysBusDevice *d = SYS_BUS_DEVICE(obj);
57 EHCISysBusState *i = SYS_BUS_EHCI(obj);
58 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
Gerd Hoffmanne4337852012-10-30 15:08:37 +010059 EHCIState *s = &i->ehci;
60
Andreas Färber4a434362012-12-16 04:49:44 +010061 s->capsbase = sec->capsbase;
62 s->opregbase = sec->opregbase;
Kuo-Jung Succ8d6a82013-06-06 15:41:12 +020063 s->portscbase = sec->portscbase;
64 s->portnr = sec->portnr;
Paolo Bonzinidf32fd12013-04-10 18:15:49 +020065 s->as = &address_space_memory;
Gerd Hoffmanne4337852012-10-30 15:08:37 +010066
Andreas Färberd4614cc2013-06-06 15:41:10 +020067 usb_ehci_init(s, DEVICE(obj));
Andreas Färber08f4c902013-06-06 15:41:09 +020068 sysbus_init_mmio(d, &s->mem);
Gerd Hoffmanne4337852012-10-30 15:08:37 +010069}
70
71static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
72{
73 DeviceClass *dc = DEVICE_CLASS(klass);
Kuo-Jung Succ8d6a82013-06-06 15:41:12 +020074 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
75
76 sec->portscbase = 0x44;
77 sec->portnr = NB_PORTS;
Gerd Hoffmanne4337852012-10-30 15:08:37 +010078
Andreas Färber08f4c902013-06-06 15:41:09 +020079 dc->realize = usb_ehci_sysbus_realize;
Gerd Hoffmanne4337852012-10-30 15:08:37 +010080 dc->vmsd = &vmstate_ehci_sysbus;
81 dc->props = ehci_sysbus_properties;
Gonglei4e289b12015-03-18 17:33:47 +080082 dc->reset = usb_ehci_sysbus_reset;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +030083 set_bit(DEVICE_CATEGORY_USB, dc->categories);
Gerd Hoffmanne4337852012-10-30 15:08:37 +010084}
85
Andreas Färber5aa3ca92012-12-16 04:49:43 +010086static const TypeInfo ehci_type_info = {
87 .name = TYPE_SYS_BUS_EHCI,
Gerd Hoffmanne4337852012-10-30 15:08:37 +010088 .parent = TYPE_SYS_BUS_DEVICE,
89 .instance_size = sizeof(EHCISysBusState),
Andreas Färberd4614cc2013-06-06 15:41:10 +020090 .instance_init = ehci_sysbus_init,
Andreas Färber5aa3ca92012-12-16 04:49:43 +010091 .abstract = true,
Gerd Hoffmanne4337852012-10-30 15:08:37 +010092 .class_init = ehci_sysbus_class_init,
Andreas Färber4a434362012-12-16 04:49:44 +010093 .class_size = sizeof(SysBusEHCIClass),
Gerd Hoffmanne4337852012-10-30 15:08:37 +010094};
95
Andreas Färber4a434362012-12-16 04:49:44 +010096static void ehci_xlnx_class_init(ObjectClass *oc, void *data)
97{
98 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +030099 DeviceClass *dc = DEVICE_CLASS(oc);
Andreas Färber4a434362012-12-16 04:49:44 +0100100
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300101 set_bit(DEVICE_CATEGORY_USB, dc->categories);
Andreas Färber4a434362012-12-16 04:49:44 +0100102 sec->capsbase = 0x100;
103 sec->opregbase = 0x140;
104}
105
Andreas Färber5aa3ca92012-12-16 04:49:43 +0100106static const TypeInfo ehci_xlnx_type_info = {
107 .name = "xlnx,ps7-usb",
108 .parent = TYPE_SYS_BUS_EHCI,
Andreas Färber4a434362012-12-16 04:49:44 +0100109 .class_init = ehci_xlnx_class_init,
Andreas Färber5aa3ca92012-12-16 04:49:43 +0100110};
111
Andreas Färberaee74992012-12-16 04:49:45 +0100112static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
113{
114 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300115 DeviceClass *dc = DEVICE_CLASS(oc);
Andreas Färberaee74992012-12-16 04:49:45 +0100116
117 sec->capsbase = 0x0;
118 sec->opregbase = 0x10;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300119 set_bit(DEVICE_CATEGORY_USB, dc->categories);
Andreas Färberaee74992012-12-16 04:49:45 +0100120}
121
122static const TypeInfo ehci_exynos4210_type_info = {
123 .name = TYPE_EXYNOS4210_EHCI,
124 .parent = TYPE_SYS_BUS_EHCI,
125 .class_init = ehci_exynos4210_class_init,
126};
127
Andreas Färber20c57042013-06-06 15:41:11 +0200128static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
129{
130 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300131 DeviceClass *dc = DEVICE_CLASS(oc);
Andreas Färber20c57042013-06-06 15:41:11 +0200132
133 sec->capsbase = 0x100;
134 sec->opregbase = 0x140;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300135 set_bit(DEVICE_CATEGORY_USB, dc->categories);
Andreas Färber20c57042013-06-06 15:41:11 +0200136}
137
138static const TypeInfo ehci_tegra2_type_info = {
139 .name = TYPE_TEGRA2_EHCI,
140 .parent = TYPE_SYS_BUS_EHCI,
141 .class_init = ehci_tegra2_class_init,
142};
143
Kuo-Jung Su4e3d8b42013-06-06 15:41:13 +0200144/*
145 * Faraday FUSBH200 USB 2.0 EHCI
146 */
147
148/**
149 * FUSBH200EHCIRegs:
150 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
151 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
152 */
153enum FUSBH200EHCIRegs {
154 FUSBH200_REG_EOF_ASTR = 0x34,
155 FUSBH200_REG_BMCSR = 0x40,
156};
157
158static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
159{
160 EHCIState *s = opaque;
161 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
162
163 switch (off) {
164 case FUSBH200_REG_EOF_ASTR:
165 return 0x00000041;
166 case FUSBH200_REG_BMCSR:
167 /* High-Speed, VBUS valid, interrupt level-high active */
168 return (2 << 9) | (1 << 8) | (1 << 3);
169 }
170
171 return 0;
172}
173
174static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
175 unsigned size)
176{
177}
178
179static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
180 .read = fusbh200_ehci_read,
181 .write = fusbh200_ehci_write,
182 .valid.min_access_size = 4,
183 .valid.max_access_size = 4,
184 .endianness = DEVICE_LITTLE_ENDIAN,
185};
186
187static void fusbh200_ehci_init(Object *obj)
188{
189 EHCISysBusState *i = SYS_BUS_EHCI(obj);
190 FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
191 EHCIState *s = &i->ehci;
192
Paolo Bonzini22fc8602013-06-06 21:25:08 -0400193 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
Kuo-Jung Su4e3d8b42013-06-06 15:41:13 +0200194 "fusbh200", 0x4c);
195 memory_region_add_subregion(&s->mem,
196 s->opregbase + s->portscbase + 4 * s->portnr,
197 &f->mem_vendor);
198}
199
200static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
201{
202 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300203 DeviceClass *dc = DEVICE_CLASS(oc);
Kuo-Jung Su4e3d8b42013-06-06 15:41:13 +0200204
205 sec->capsbase = 0x0;
206 sec->opregbase = 0x10;
207 sec->portscbase = 0x20;
208 sec->portnr = 1;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300209 set_bit(DEVICE_CATEGORY_USB, dc->categories);
Kuo-Jung Su4e3d8b42013-06-06 15:41:13 +0200210}
211
212static const TypeInfo ehci_fusbh200_type_info = {
213 .name = TYPE_FUSBH200_EHCI,
214 .parent = TYPE_SYS_BUS_EHCI,
215 .instance_size = sizeof(FUSBH200EHCIState),
216 .instance_init = fusbh200_ehci_init,
217 .class_init = fusbh200_ehci_class_init,
218};
219
Gerd Hoffmanne4337852012-10-30 15:08:37 +0100220static void ehci_sysbus_register_types(void)
221{
Andreas Färber5aa3ca92012-12-16 04:49:43 +0100222 type_register_static(&ehci_type_info);
Gerd Hoffmanne4337852012-10-30 15:08:37 +0100223 type_register_static(&ehci_xlnx_type_info);
Andreas Färberaee74992012-12-16 04:49:45 +0100224 type_register_static(&ehci_exynos4210_type_info);
Andreas Färber20c57042013-06-06 15:41:11 +0200225 type_register_static(&ehci_tegra2_type_info);
Kuo-Jung Su4e3d8b42013-06-06 15:41:13 +0200226 type_register_static(&ehci_fusbh200_type_info);
Gerd Hoffmanne4337852012-10-30 15:08:37 +0100227}
228
229type_init(ehci_sysbus_register_types)