bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Sparc SLAVIO timer controller emulation |
| 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 24 | |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 25 | #include "hw/sparc/sun4m.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 26 | #include "qemu/timer.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 27 | #include "hw/ptimer.h" |
| 28 | #include "hw/sysbus.h" |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 29 | #include "trace.h" |
Alex Bligh | 6a1751b | 2013-08-21 16:02:47 +0100 | [diff] [blame] | 30 | #include "qemu/main-loop.h" |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 31 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 32 | /* |
| 33 | * Registers of hardware timer in sun4m. |
| 34 | * |
| 35 | * This is the timer/counter part of chip STP2001 (Slave I/O), also |
| 36 | * produced as NCR89C105. See |
| 37 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 38 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 39 | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 |
| 40 | * are zero. Bit 31 is 1 when count has been reached. |
| 41 | * |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 42 | * Per-CPU timers interrupt local CPU, system timer uses normal |
| 43 | * interrupt routing. |
| 44 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 47 | #define MAX_CPUS 16 |
| 48 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 49 | typedef struct CPUTimerState { |
blueswir1 | d7edfd2 | 2007-05-27 16:37:49 +0000 | [diff] [blame] | 50 | qemu_irq irq; |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 51 | ptimer_state *timer; |
| 52 | uint32_t count, counthigh, reached; |
Blue Swirl | f90074f | 2011-08-07 19:00:23 +0000 | [diff] [blame] | 53 | /* processor only */ |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 54 | uint32_t run; |
Blue Swirl | f90074f | 2011-08-07 19:00:23 +0000 | [diff] [blame] | 55 | uint64_t limit; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 56 | } CPUTimerState; |
| 57 | |
Andreas Färber | c275471 | 2013-07-27 15:24:22 +0200 | [diff] [blame] | 58 | #define TYPE_SLAVIO_TIMER "slavio_timer" |
| 59 | #define SLAVIO_TIMER(obj) \ |
| 60 | OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER) |
| 61 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 62 | typedef struct SLAVIO_TIMERState { |
Andreas Färber | c275471 | 2013-07-27 15:24:22 +0200 | [diff] [blame] | 63 | SysBusDevice parent_obj; |
| 64 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 65 | uint32_t num_cpus; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 66 | uint32_t cputimer_mode; |
Blue Swirl | f90074f | 2011-08-07 19:00:23 +0000 | [diff] [blame] | 67 | CPUTimerState cputimer[MAX_CPUS + 1]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 68 | } SLAVIO_TIMERState; |
| 69 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 70 | typedef struct TimerContext { |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 71 | MemoryRegion iomem; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 72 | SLAVIO_TIMERState *s; |
| 73 | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ |
| 74 | } TimerContext; |
| 75 | |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 76 | #define SYS_TIMER_SIZE 0x14 |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 77 | #define CPU_TIMER_SIZE 0x10 |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 78 | |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 79 | #define TIMER_LIMIT 0 |
| 80 | #define TIMER_COUNTER 1 |
| 81 | #define TIMER_COUNTER_NORST 2 |
| 82 | #define TIMER_STATUS 3 |
| 83 | #define TIMER_MODE 4 |
| 84 | |
| 85 | #define TIMER_COUNT_MASK32 0xfffffe00 |
| 86 | #define TIMER_LIMIT_MASK32 0x7fffffff |
| 87 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
| 88 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
| 89 | #define TIMER_REACHED 0x80000000 |
| 90 | #define TIMER_PERIOD 500ULL // 500ns |
Blue Swirl | 68fb89a | 2010-04-03 06:17:35 +0000 | [diff] [blame] | 91 | #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) |
| 92 | #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 93 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 94 | static int slavio_timer_is_user(TimerContext *tc) |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 95 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 96 | SLAVIO_TIMERState *s = tc->s; |
| 97 | unsigned int timer_index = tc->timer_index; |
| 98 | |
| 99 | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 100 | } |
| 101 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 102 | // Update count, set irq, update expire_time |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 103 | // Convert from ptimer countdown units |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 104 | static void slavio_timer_get_out(CPUTimerState *t) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 105 | { |
blueswir1 | bd7e287 | 2007-12-19 17:58:24 +0000 | [diff] [blame] | 106 | uint64_t count, limit; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 107 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 108 | if (t->limit == 0) { /* free-run system or processor counter */ |
blueswir1 | bd7e287 | 2007-12-19 17:58:24 +0000 | [diff] [blame] | 109 | limit = TIMER_MAX_COUNT32; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 110 | } else { |
| 111 | limit = t->limit; |
| 112 | } |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 113 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
| 114 | |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 115 | trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 116 | t->count = count & TIMER_COUNT_MASK32; |
| 117 | t->counthigh = count >> 32; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | // timer callback |
| 121 | static void slavio_timer_irq(void *opaque) |
| 122 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 123 | TimerContext *tc = opaque; |
| 124 | SLAVIO_TIMERState *s = tc->s; |
| 125 | CPUTimerState *t = &s->cputimer[tc->timer_index]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 126 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 127 | slavio_timer_get_out(t); |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 128 | trace_slavio_timer_irq(t->counthigh, t->count); |
Blue Swirl | 68fb89a | 2010-04-03 06:17:35 +0000 | [diff] [blame] | 129 | /* if limit is 0 (free-run), there will be no match */ |
| 130 | if (t->limit != 0) { |
| 131 | t->reached = TIMER_REACHED; |
| 132 | } |
Blue Swirl | 452efba | 2010-01-24 14:28:21 +0000 | [diff] [blame] | 133 | /* there is no interrupt if user timer or free-run */ |
| 134 | if (!slavio_timer_is_user(tc) && t->limit != 0) { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 135 | qemu_irq_raise(t->irq); |
| 136 | } |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 137 | } |
| 138 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 139 | static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr, |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 140 | unsigned size) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 141 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 142 | TimerContext *tc = opaque; |
| 143 | SLAVIO_TIMERState *s = tc->s; |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 144 | uint32_t saddr, ret; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 145 | unsigned int timer_index = tc->timer_index; |
| 146 | CPUTimerState *t = &s->cputimer[timer_index]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 147 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 148 | saddr = addr >> 2; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 149 | switch (saddr) { |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 150 | case TIMER_LIMIT: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 151 | // read limit (system counter mode) or read most signifying |
| 152 | // part of counter (user mode) |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 153 | if (slavio_timer_is_user(tc)) { |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 154 | // read user timer MSW |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 155 | slavio_timer_get_out(t); |
| 156 | ret = t->counthigh | t->reached; |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 157 | } else { |
| 158 | // read limit |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 159 | // clear irq |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 160 | qemu_irq_lower(t->irq); |
| 161 | t->reached = 0; |
| 162 | ret = t->limit & TIMER_LIMIT_MASK32; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 163 | } |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 164 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 165 | case TIMER_COUNTER: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 166 | // read counter and reached bit (system mode) or read lsbits |
| 167 | // of counter (user mode) |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 168 | slavio_timer_get_out(t); |
| 169 | if (slavio_timer_is_user(tc)) { // read user timer LSW |
| 170 | ret = t->count & TIMER_MAX_COUNT64; |
| 171 | } else { // read limit |
| 172 | ret = (t->count & TIMER_MAX_COUNT32) | |
| 173 | t->reached; |
| 174 | } |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 175 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 176 | case TIMER_STATUS: |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 177 | // only available in processor counter/timer |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 178 | // read start/stop status |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 179 | if (timer_index > 0) { |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 180 | ret = t->run; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 181 | } else { |
| 182 | ret = 0; |
| 183 | } |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 184 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 185 | case TIMER_MODE: |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 186 | // only available in system counter |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 187 | // read user/system mode |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 188 | ret = s->cputimer_mode; |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 189 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 190 | default: |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 191 | trace_slavio_timer_mem_readl_invalid(addr); |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 192 | ret = 0; |
| 193 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 194 | } |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 195 | trace_slavio_timer_mem_readl(addr, ret); |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 196 | return ret; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 197 | } |
| 198 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 199 | static void slavio_timer_mem_writel(void *opaque, hwaddr addr, |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 200 | uint64_t val, unsigned size) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 201 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 202 | TimerContext *tc = opaque; |
| 203 | SLAVIO_TIMERState *s = tc->s; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 204 | uint32_t saddr; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 205 | unsigned int timer_index = tc->timer_index; |
| 206 | CPUTimerState *t = &s->cputimer[timer_index]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 207 | |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 208 | trace_slavio_timer_mem_writel(addr, val); |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 209 | saddr = addr >> 2; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 210 | switch (saddr) { |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 211 | case TIMER_LIMIT: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 212 | if (slavio_timer_is_user(tc)) { |
blueswir1 | e1cb950 | 2008-01-25 19:51:27 +0000 | [diff] [blame] | 213 | uint64_t count; |
| 214 | |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 215 | // set user counter MSW, reset counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 216 | t->limit = TIMER_MAX_COUNT64; |
| 217 | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); |
| 218 | t->reached = 0; |
| 219 | count = ((uint64_t)t->counthigh << 32) | t->count; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 220 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 221 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 222 | } else { |
| 223 | // set limit, reset counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 224 | qemu_irq_lower(t->irq); |
| 225 | t->limit = val & TIMER_MAX_COUNT32; |
| 226 | if (t->timer) { |
| 227 | if (t->limit == 0) { /* free-run */ |
| 228 | ptimer_set_limit(t->timer, |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 229 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 230 | } else { |
| 231 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); |
| 232 | } |
blueswir1 | 85e3023 | 2007-12-27 20:23:20 +0000 | [diff] [blame] | 233 | } |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 234 | } |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 235 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 236 | case TIMER_COUNTER: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 237 | if (slavio_timer_is_user(tc)) { |
blueswir1 | e1cb950 | 2008-01-25 19:51:27 +0000 | [diff] [blame] | 238 | uint64_t count; |
| 239 | |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 240 | // set user counter LSW, reset counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 241 | t->limit = TIMER_MAX_COUNT64; |
| 242 | t->count = val & TIMER_MAX_COUNT64; |
| 243 | t->reached = 0; |
| 244 | count = ((uint64_t)t->counthigh) << 32 | t->count; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 245 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 246 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 247 | } else { |
| 248 | trace_slavio_timer_mem_writel_counter_invalid(); |
| 249 | } |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 250 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 251 | case TIMER_COUNTER_NORST: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 252 | // set limit without resetting counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 253 | t->limit = val & TIMER_MAX_COUNT32; |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 254 | if (t->limit == 0) { /* free-run */ |
| 255 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); |
| 256 | } else { |
| 257 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); |
blueswir1 | 85e3023 | 2007-12-27 20:23:20 +0000 | [diff] [blame] | 258 | } |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 259 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 260 | case TIMER_STATUS: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 261 | if (slavio_timer_is_user(tc)) { |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 262 | // start/stop user counter |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 263 | if (val & 1) { |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 264 | trace_slavio_timer_mem_writel_status_start(timer_index); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 265 | ptimer_run(t->timer, 0); |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 266 | } else { |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 267 | trace_slavio_timer_mem_writel_status_stop(timer_index); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 268 | ptimer_stop(t->timer); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 269 | } |
| 270 | } |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 271 | t->run = val & 1; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 272 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 273 | case TIMER_MODE: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 274 | if (timer_index == 0) { |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 275 | unsigned int i; |
| 276 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 277 | for (i = 0; i < s->num_cpus; i++) { |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 278 | unsigned int processor = 1 << i; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 279 | CPUTimerState *curr_timer = &s->cputimer[i + 1]; |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 280 | |
| 281 | // check for a change in timer mode for this processor |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 282 | if ((val & processor) != (s->cputimer_mode & processor)) { |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 283 | if (val & processor) { // counter -> user timer |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 284 | qemu_irq_lower(curr_timer->irq); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 285 | // counters are always running |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 286 | if (!curr_timer->run) { |
| 287 | ptimer_stop(curr_timer->timer); |
| 288 | } |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 289 | // user timer limit is always the same |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 290 | curr_timer->limit = TIMER_MAX_COUNT64; |
| 291 | ptimer_set_limit(curr_timer->timer, |
| 292 | LIMIT_TO_PERIODS(curr_timer->limit), |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 293 | 1); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 294 | // set this processors user timer bit in config |
| 295 | // register |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 296 | s->cputimer_mode |= processor; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 297 | trace_slavio_timer_mem_writel_mode_user(timer_index); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 298 | } else { // user timer -> counter |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 299 | // start the counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 300 | ptimer_run(curr_timer->timer, 0); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 301 | // clear this processors user timer bit in config |
| 302 | // register |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 303 | s->cputimer_mode &= ~processor; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 304 | trace_slavio_timer_mem_writel_mode_counter(timer_index); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 305 | } |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 306 | } |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 307 | } |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 308 | } else { |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 309 | trace_slavio_timer_mem_writel_mode_invalid(); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 310 | } |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 311 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 312 | default: |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 313 | trace_slavio_timer_mem_writel_invalid(addr); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 314 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 315 | } |
| 316 | } |
| 317 | |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 318 | static const MemoryRegionOps slavio_timer_mem_ops = { |
| 319 | .read = slavio_timer_mem_readl, |
| 320 | .write = slavio_timer_mem_writel, |
| 321 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 322 | .valid = { |
| 323 | .min_access_size = 4, |
| 324 | .max_access_size = 4, |
| 325 | }, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 326 | }; |
| 327 | |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 328 | static const VMStateDescription vmstate_timer = { |
| 329 | .name ="timer", |
| 330 | .version_id = 3, |
| 331 | .minimum_version_id = 3, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 332 | .fields = (VMStateField[]) { |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 333 | VMSTATE_UINT64(limit, CPUTimerState), |
| 334 | VMSTATE_UINT32(count, CPUTimerState), |
| 335 | VMSTATE_UINT32(counthigh, CPUTimerState), |
| 336 | VMSTATE_UINT32(reached, CPUTimerState), |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 337 | VMSTATE_UINT32(run , CPUTimerState), |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 338 | VMSTATE_PTIMER(timer, CPUTimerState), |
| 339 | VMSTATE_END_OF_LIST() |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 340 | } |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 341 | }; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 342 | |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 343 | static const VMStateDescription vmstate_slavio_timer = { |
| 344 | .name ="slavio_timer", |
| 345 | .version_id = 3, |
| 346 | .minimum_version_id = 3, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 347 | .fields = (VMStateField[]) { |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 348 | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, |
| 349 | vmstate_timer, CPUTimerState), |
| 350 | VMSTATE_END_OF_LIST() |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 351 | } |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 352 | }; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 353 | |
Blue Swirl | 0e0bfee | 2009-10-24 17:35:13 +0000 | [diff] [blame] | 354 | static void slavio_timer_reset(DeviceState *d) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 355 | { |
Andreas Färber | c275471 | 2013-07-27 15:24:22 +0200 | [diff] [blame] | 356 | SLAVIO_TIMERState *s = SLAVIO_TIMER(d); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 357 | unsigned int i; |
| 358 | CPUTimerState *curr_timer; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 359 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 360 | for (i = 0; i <= MAX_CPUS; i++) { |
| 361 | curr_timer = &s->cputimer[i]; |
| 362 | curr_timer->limit = 0; |
| 363 | curr_timer->count = 0; |
| 364 | curr_timer->reached = 0; |
Artyom Tarasenko | 5933e8a | 2010-08-02 19:58:21 +0200 | [diff] [blame] | 365 | if (i <= s->num_cpus) { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 366 | ptimer_set_limit(curr_timer->timer, |
| 367 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
| 368 | ptimer_run(curr_timer->timer, 0); |
Mark Cave-Ayland | ead4cf0 | 2014-02-22 22:54:53 +0000 | [diff] [blame] | 369 | curr_timer->run = 1; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 370 | } |
blueswir1 | 85e3023 | 2007-12-27 20:23:20 +0000 | [diff] [blame] | 371 | } |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 372 | s->cputimer_mode = 0; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 373 | } |
| 374 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 375 | static int slavio_timer_init1(SysBusDevice *dev) |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 376 | { |
Andreas Färber | c275471 | 2013-07-27 15:24:22 +0200 | [diff] [blame] | 377 | SLAVIO_TIMERState *s = SLAVIO_TIMER(dev); |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 378 | QEMUBH *bh; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 379 | unsigned int i; |
| 380 | TimerContext *tc; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 381 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 382 | for (i = 0; i <= MAX_CPUS; i++) { |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 383 | uint64_t size; |
| 384 | char timer_name[20]; |
| 385 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 386 | tc = g_malloc0(sizeof(TimerContext)); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 387 | tc->s = s; |
| 388 | tc->timer_index = i; |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 389 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 390 | bh = qemu_bh_new(slavio_timer_irq, tc); |
| 391 | s->cputimer[i].timer = ptimer_init(bh); |
| 392 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 393 | |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 394 | size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; |
| 395 | snprintf(timer_name, sizeof(timer_name), "timer-%i", i); |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 396 | memory_region_init_io(&tc->iomem, OBJECT(s), &slavio_timer_mem_ops, tc, |
Benoît Canet | a3d12d0 | 2011-11-15 12:14:02 +0100 | [diff] [blame] | 397 | timer_name, size); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 398 | sysbus_init_mmio(dev, &tc->iomem); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 399 | |
| 400 | sysbus_init_irq(dev, &s->cputimer[i].irq); |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 401 | } |
| 402 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 403 | return 0; |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 404 | } |
| 405 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 406 | static Property slavio_timer_properties[] = { |
| 407 | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
| 408 | DEFINE_PROP_END_OF_LIST(), |
| 409 | }; |
| 410 | |
| 411 | static void slavio_timer_class_init(ObjectClass *klass, void *data) |
| 412 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 413 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 414 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 415 | |
| 416 | k->init = slavio_timer_init1; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 417 | dc->reset = slavio_timer_reset; |
| 418 | dc->vmsd = &vmstate_slavio_timer; |
| 419 | dc->props = slavio_timer_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 420 | } |
| 421 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 422 | static const TypeInfo slavio_timer_info = { |
Andreas Färber | c275471 | 2013-07-27 15:24:22 +0200 | [diff] [blame] | 423 | .name = TYPE_SLAVIO_TIMER, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 424 | .parent = TYPE_SYS_BUS_DEVICE, |
| 425 | .instance_size = sizeof(SLAVIO_TIMERState), |
| 426 | .class_init = slavio_timer_class_init, |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 427 | }; |
| 428 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 429 | static void slavio_timer_register_types(void) |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 430 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 431 | type_register_static(&slavio_timer_info); |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 432 | } |
| 433 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 434 | type_init(slavio_timer_register_types) |