blob: 45d97e667839ea6483c8e5f98053175ca5baf158 [file] [log] [blame]
bellarde80cfcf2004-12-19 23:18:01 +00001/*
2 * QEMU Sparc SLAVIO timer controller emulation
3 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellarde80cfcf2004-12-19 23:18:01 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirlc70c59e2009-07-15 08:53:09 +000024
Paolo Bonzini0d09e412013-02-05 17:06:20 +010025#include "hw/sparc/sun4m.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010026#include "qemu/timer.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010027#include "hw/ptimer.h"
28#include "hw/sysbus.h"
Blue Swirl97bf4852010-10-31 09:24:14 +000029#include "trace.h"
Alex Bligh6a1751b2013-08-21 16:02:47 +010030#include "qemu/main-loop.h"
bellard66321a12005-04-06 20:47:48 +000031
bellarde80cfcf2004-12-19 23:18:01 +000032/*
33 * Registers of hardware timer in sun4m.
34 *
35 * This is the timer/counter part of chip STP2001 (Slave I/O), also
36 * produced as NCR89C105. See
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
ths5fafdf22007-09-16 21:08:06 +000038 *
bellarde80cfcf2004-12-19 23:18:01 +000039 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
40 * are zero. Bit 31 is 1 when count has been reached.
41 *
bellardba3c64f2005-12-05 20:31:52 +000042 * Per-CPU timers interrupt local CPU, system timer uses normal
43 * interrupt routing.
44 *
bellarde80cfcf2004-12-19 23:18:01 +000045 */
46
blueswir181732d12007-10-06 11:25:43 +000047#define MAX_CPUS 16
48
Blue Swirl7204ff92009-08-08 20:08:15 +000049typedef struct CPUTimerState {
blueswir1d7edfd22007-05-27 16:37:49 +000050 qemu_irq irq;
blueswir18d05ea82007-05-24 19:48:41 +000051 ptimer_state *timer;
52 uint32_t count, counthigh, reached;
Blue Swirlf90074f2011-08-07 19:00:23 +000053 /* processor only */
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +000054 uint32_t run;
Blue Swirlf90074f2011-08-07 19:00:23 +000055 uint64_t limit;
Blue Swirl7204ff92009-08-08 20:08:15 +000056} CPUTimerState;
57
Andreas Färberc2754712013-07-27 15:24:22 +020058#define TYPE_SLAVIO_TIMER "slavio_timer"
59#define SLAVIO_TIMER(obj) \
60 OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER)
61
Blue Swirl7204ff92009-08-08 20:08:15 +000062typedef struct SLAVIO_TIMERState {
Andreas Färberc2754712013-07-27 15:24:22 +020063 SysBusDevice parent_obj;
64
Blue Swirl7204ff92009-08-08 20:08:15 +000065 uint32_t num_cpus;
Blue Swirl7204ff92009-08-08 20:08:15 +000066 uint32_t cputimer_mode;
Blue Swirlf90074f2011-08-07 19:00:23 +000067 CPUTimerState cputimer[MAX_CPUS + 1];
bellarde80cfcf2004-12-19 23:18:01 +000068} SLAVIO_TIMERState;
69
Blue Swirl7204ff92009-08-08 20:08:15 +000070typedef struct TimerContext {
Benoît Caneta3d12d02011-11-15 12:14:02 +010071 MemoryRegion iomem;
Blue Swirl7204ff92009-08-08 20:08:15 +000072 SLAVIO_TIMERState *s;
73 unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
74} TimerContext;
75
blueswir1115646b2007-10-07 10:00:55 +000076#define SYS_TIMER_SIZE 0x14
blueswir181732d12007-10-06 11:25:43 +000077#define CPU_TIMER_SIZE 0x10
bellarde80cfcf2004-12-19 23:18:01 +000078
blueswir1d2c38b22007-12-01 15:58:22 +000079#define TIMER_LIMIT 0
80#define TIMER_COUNTER 1
81#define TIMER_COUNTER_NORST 2
82#define TIMER_STATUS 3
83#define TIMER_MODE 4
84
85#define TIMER_COUNT_MASK32 0xfffffe00
86#define TIMER_LIMIT_MASK32 0x7fffffff
87#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
88#define TIMER_MAX_COUNT32 0x7ffffe00ULL
89#define TIMER_REACHED 0x80000000
90#define TIMER_PERIOD 500ULL // 500ns
Blue Swirl68fb89a2010-04-03 06:17:35 +000091#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
92#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
blueswir1d2c38b22007-12-01 15:58:22 +000093
Blue Swirl7204ff92009-08-08 20:08:15 +000094static int slavio_timer_is_user(TimerContext *tc)
blueswir1115646b2007-10-07 10:00:55 +000095{
Blue Swirl7204ff92009-08-08 20:08:15 +000096 SLAVIO_TIMERState *s = tc->s;
97 unsigned int timer_index = tc->timer_index;
98
99 return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
blueswir1115646b2007-10-07 10:00:55 +0000100}
101
bellarde80cfcf2004-12-19 23:18:01 +0000102// Update count, set irq, update expire_time
blueswir18d05ea82007-05-24 19:48:41 +0000103// Convert from ptimer countdown units
Blue Swirl7204ff92009-08-08 20:08:15 +0000104static void slavio_timer_get_out(CPUTimerState *t)
bellarde80cfcf2004-12-19 23:18:01 +0000105{
blueswir1bd7e2872007-12-19 17:58:24 +0000106 uint64_t count, limit;
bellarde80cfcf2004-12-19 23:18:01 +0000107
Blue Swirl7204ff92009-08-08 20:08:15 +0000108 if (t->limit == 0) { /* free-run system or processor counter */
blueswir1bd7e2872007-12-19 17:58:24 +0000109 limit = TIMER_MAX_COUNT32;
Blue Swirl7204ff92009-08-08 20:08:15 +0000110 } else {
111 limit = t->limit;
112 }
Blue Swirl9ebec282009-08-31 19:30:17 +0000113 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
114
Blue Swirl97bf4852010-10-31 09:24:14 +0000115 trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
Blue Swirl7204ff92009-08-08 20:08:15 +0000116 t->count = count & TIMER_COUNT_MASK32;
117 t->counthigh = count >> 32;
bellarde80cfcf2004-12-19 23:18:01 +0000118}
119
120// timer callback
121static void slavio_timer_irq(void *opaque)
122{
Blue Swirl7204ff92009-08-08 20:08:15 +0000123 TimerContext *tc = opaque;
124 SLAVIO_TIMERState *s = tc->s;
125 CPUTimerState *t = &s->cputimer[tc->timer_index];
bellarde80cfcf2004-12-19 23:18:01 +0000126
Blue Swirl7204ff92009-08-08 20:08:15 +0000127 slavio_timer_get_out(t);
Blue Swirl97bf4852010-10-31 09:24:14 +0000128 trace_slavio_timer_irq(t->counthigh, t->count);
Blue Swirl68fb89a2010-04-03 06:17:35 +0000129 /* if limit is 0 (free-run), there will be no match */
130 if (t->limit != 0) {
131 t->reached = TIMER_REACHED;
132 }
Blue Swirl452efba2010-01-24 14:28:21 +0000133 /* there is no interrupt if user timer or free-run */
134 if (!slavio_timer_is_user(tc) && t->limit != 0) {
Blue Swirl7204ff92009-08-08 20:08:15 +0000135 qemu_irq_raise(t->irq);
136 }
bellarde80cfcf2004-12-19 23:18:01 +0000137}
138
Avi Kivitya8170e52012-10-23 12:30:10 +0200139static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
Benoît Caneta3d12d02011-11-15 12:14:02 +0100140 unsigned size)
bellarde80cfcf2004-12-19 23:18:01 +0000141{
Blue Swirl7204ff92009-08-08 20:08:15 +0000142 TimerContext *tc = opaque;
143 SLAVIO_TIMERState *s = tc->s;
blueswir18d05ea82007-05-24 19:48:41 +0000144 uint32_t saddr, ret;
Blue Swirl7204ff92009-08-08 20:08:15 +0000145 unsigned int timer_index = tc->timer_index;
146 CPUTimerState *t = &s->cputimer[timer_index];
bellarde80cfcf2004-12-19 23:18:01 +0000147
blueswir1e64d7d52008-12-02 17:47:02 +0000148 saddr = addr >> 2;
bellarde80cfcf2004-12-19 23:18:01 +0000149 switch (saddr) {
blueswir1d2c38b22007-12-01 15:58:22 +0000150 case TIMER_LIMIT:
blueswir1f930d072007-10-06 11:28:21 +0000151 // read limit (system counter mode) or read most signifying
152 // part of counter (user mode)
Blue Swirl7204ff92009-08-08 20:08:15 +0000153 if (slavio_timer_is_user(tc)) {
blueswir1115646b2007-10-07 10:00:55 +0000154 // read user timer MSW
Blue Swirl7204ff92009-08-08 20:08:15 +0000155 slavio_timer_get_out(t);
156 ret = t->counthigh | t->reached;
blueswir1115646b2007-10-07 10:00:55 +0000157 } else {
158 // read limit
blueswir1f930d072007-10-06 11:28:21 +0000159 // clear irq
Blue Swirl7204ff92009-08-08 20:08:15 +0000160 qemu_irq_lower(t->irq);
161 t->reached = 0;
162 ret = t->limit & TIMER_LIMIT_MASK32;
blueswir1f930d072007-10-06 11:28:21 +0000163 }
blueswir18d05ea82007-05-24 19:48:41 +0000164 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000165 case TIMER_COUNTER:
blueswir1f930d072007-10-06 11:28:21 +0000166 // read counter and reached bit (system mode) or read lsbits
167 // of counter (user mode)
Blue Swirl7204ff92009-08-08 20:08:15 +0000168 slavio_timer_get_out(t);
169 if (slavio_timer_is_user(tc)) { // read user timer LSW
170 ret = t->count & TIMER_MAX_COUNT64;
171 } else { // read limit
172 ret = (t->count & TIMER_MAX_COUNT32) |
173 t->reached;
174 }
blueswir18d05ea82007-05-24 19:48:41 +0000175 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000176 case TIMER_STATUS:
blueswir1115646b2007-10-07 10:00:55 +0000177 // only available in processor counter/timer
blueswir1f930d072007-10-06 11:28:21 +0000178 // read start/stop status
Blue Swirl7204ff92009-08-08 20:08:15 +0000179 if (timer_index > 0) {
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000180 ret = t->run;
Blue Swirl7204ff92009-08-08 20:08:15 +0000181 } else {
182 ret = 0;
183 }
blueswir18d05ea82007-05-24 19:48:41 +0000184 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000185 case TIMER_MODE:
blueswir1115646b2007-10-07 10:00:55 +0000186 // only available in system counter
blueswir1f930d072007-10-06 11:28:21 +0000187 // read user/system mode
Blue Swirl7204ff92009-08-08 20:08:15 +0000188 ret = s->cputimer_mode;
blueswir18d05ea82007-05-24 19:48:41 +0000189 break;
bellarde80cfcf2004-12-19 23:18:01 +0000190 default:
Blue Swirl97bf4852010-10-31 09:24:14 +0000191 trace_slavio_timer_mem_readl_invalid(addr);
blueswir18d05ea82007-05-24 19:48:41 +0000192 ret = 0;
193 break;
bellarde80cfcf2004-12-19 23:18:01 +0000194 }
Blue Swirl97bf4852010-10-31 09:24:14 +0000195 trace_slavio_timer_mem_readl(addr, ret);
blueswir18d05ea82007-05-24 19:48:41 +0000196 return ret;
bellarde80cfcf2004-12-19 23:18:01 +0000197}
198
Avi Kivitya8170e52012-10-23 12:30:10 +0200199static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
Benoît Caneta3d12d02011-11-15 12:14:02 +0100200 uint64_t val, unsigned size)
bellarde80cfcf2004-12-19 23:18:01 +0000201{
Blue Swirl7204ff92009-08-08 20:08:15 +0000202 TimerContext *tc = opaque;
203 SLAVIO_TIMERState *s = tc->s;
bellarde80cfcf2004-12-19 23:18:01 +0000204 uint32_t saddr;
Blue Swirl7204ff92009-08-08 20:08:15 +0000205 unsigned int timer_index = tc->timer_index;
206 CPUTimerState *t = &s->cputimer[timer_index];
bellarde80cfcf2004-12-19 23:18:01 +0000207
Blue Swirl97bf4852010-10-31 09:24:14 +0000208 trace_slavio_timer_mem_writel(addr, val);
blueswir1e64d7d52008-12-02 17:47:02 +0000209 saddr = addr >> 2;
bellarde80cfcf2004-12-19 23:18:01 +0000210 switch (saddr) {
blueswir1d2c38b22007-12-01 15:58:22 +0000211 case TIMER_LIMIT:
Blue Swirl7204ff92009-08-08 20:08:15 +0000212 if (slavio_timer_is_user(tc)) {
blueswir1e1cb9502008-01-25 19:51:27 +0000213 uint64_t count;
214
blueswir1115646b2007-10-07 10:00:55 +0000215 // set user counter MSW, reset counter
Blue Swirl7204ff92009-08-08 20:08:15 +0000216 t->limit = TIMER_MAX_COUNT64;
217 t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
218 t->reached = 0;
219 count = ((uint64_t)t->counthigh << 32) | t->count;
Blue Swirl97bf4852010-10-31 09:24:14 +0000220 trace_slavio_timer_mem_writel_limit(timer_index, count);
Blue Swirl9ebec282009-08-31 19:30:17 +0000221 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
blueswir1115646b2007-10-07 10:00:55 +0000222 } else {
223 // set limit, reset counter
Blue Swirl7204ff92009-08-08 20:08:15 +0000224 qemu_irq_lower(t->irq);
225 t->limit = val & TIMER_MAX_COUNT32;
226 if (t->timer) {
227 if (t->limit == 0) { /* free-run */
228 ptimer_set_limit(t->timer,
blueswir177f193d2008-05-12 16:13:33 +0000229 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
Blue Swirl7204ff92009-08-08 20:08:15 +0000230 } else {
231 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
232 }
blueswir185e30232007-12-27 20:23:20 +0000233 }
blueswir181732d12007-10-06 11:25:43 +0000234 }
blueswir1115646b2007-10-07 10:00:55 +0000235 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000236 case TIMER_COUNTER:
Blue Swirl7204ff92009-08-08 20:08:15 +0000237 if (slavio_timer_is_user(tc)) {
blueswir1e1cb9502008-01-25 19:51:27 +0000238 uint64_t count;
239
blueswir1115646b2007-10-07 10:00:55 +0000240 // set user counter LSW, reset counter
Blue Swirl7204ff92009-08-08 20:08:15 +0000241 t->limit = TIMER_MAX_COUNT64;
242 t->count = val & TIMER_MAX_COUNT64;
243 t->reached = 0;
244 count = ((uint64_t)t->counthigh) << 32 | t->count;
Blue Swirl97bf4852010-10-31 09:24:14 +0000245 trace_slavio_timer_mem_writel_limit(timer_index, count);
Blue Swirl9ebec282009-08-31 19:30:17 +0000246 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
Blue Swirl97bf4852010-10-31 09:24:14 +0000247 } else {
248 trace_slavio_timer_mem_writel_counter_invalid();
249 }
blueswir1115646b2007-10-07 10:00:55 +0000250 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000251 case TIMER_COUNTER_NORST:
blueswir1f930d072007-10-06 11:28:21 +0000252 // set limit without resetting counter
Blue Swirl7204ff92009-08-08 20:08:15 +0000253 t->limit = val & TIMER_MAX_COUNT32;
Blue Swirl9ebec282009-08-31 19:30:17 +0000254 if (t->limit == 0) { /* free-run */
255 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
256 } else {
257 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
blueswir185e30232007-12-27 20:23:20 +0000258 }
blueswir1f930d072007-10-06 11:28:21 +0000259 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000260 case TIMER_STATUS:
Blue Swirl7204ff92009-08-08 20:08:15 +0000261 if (slavio_timer_is_user(tc)) {
blueswir1115646b2007-10-07 10:00:55 +0000262 // start/stop user counter
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000263 if (val & 1) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000264 trace_slavio_timer_mem_writel_status_start(timer_index);
Blue Swirl9ebec282009-08-31 19:30:17 +0000265 ptimer_run(t->timer, 0);
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000266 } else {
Blue Swirl97bf4852010-10-31 09:24:14 +0000267 trace_slavio_timer_mem_writel_status_stop(timer_index);
Blue Swirl9ebec282009-08-31 19:30:17 +0000268 ptimer_stop(t->timer);
blueswir1f930d072007-10-06 11:28:21 +0000269 }
270 }
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000271 t->run = val & 1;
blueswir1f930d072007-10-06 11:28:21 +0000272 break;
blueswir1d2c38b22007-12-01 15:58:22 +0000273 case TIMER_MODE:
Blue Swirl7204ff92009-08-08 20:08:15 +0000274 if (timer_index == 0) {
blueswir181732d12007-10-06 11:25:43 +0000275 unsigned int i;
276
Blue Swirl7204ff92009-08-08 20:08:15 +0000277 for (i = 0; i < s->num_cpus; i++) {
blueswir167e42752008-01-26 09:13:46 +0000278 unsigned int processor = 1 << i;
Blue Swirl7204ff92009-08-08 20:08:15 +0000279 CPUTimerState *curr_timer = &s->cputimer[i + 1];
blueswir167e42752008-01-26 09:13:46 +0000280
281 // check for a change in timer mode for this processor
Blue Swirl7204ff92009-08-08 20:08:15 +0000282 if ((val & processor) != (s->cputimer_mode & processor)) {
blueswir167e42752008-01-26 09:13:46 +0000283 if (val & processor) { // counter -> user timer
Blue Swirl7204ff92009-08-08 20:08:15 +0000284 qemu_irq_lower(curr_timer->irq);
blueswir167e42752008-01-26 09:13:46 +0000285 // counters are always running
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000286 if (!curr_timer->run) {
287 ptimer_stop(curr_timer->timer);
288 }
blueswir167e42752008-01-26 09:13:46 +0000289 // user timer limit is always the same
Blue Swirl7204ff92009-08-08 20:08:15 +0000290 curr_timer->limit = TIMER_MAX_COUNT64;
291 ptimer_set_limit(curr_timer->timer,
292 LIMIT_TO_PERIODS(curr_timer->limit),
blueswir177f193d2008-05-12 16:13:33 +0000293 1);
blueswir167e42752008-01-26 09:13:46 +0000294 // set this processors user timer bit in config
295 // register
Blue Swirl7204ff92009-08-08 20:08:15 +0000296 s->cputimer_mode |= processor;
Blue Swirl97bf4852010-10-31 09:24:14 +0000297 trace_slavio_timer_mem_writel_mode_user(timer_index);
blueswir167e42752008-01-26 09:13:46 +0000298 } else { // user timer -> counter
blueswir167e42752008-01-26 09:13:46 +0000299 // start the counter
Blue Swirl7204ff92009-08-08 20:08:15 +0000300 ptimer_run(curr_timer->timer, 0);
blueswir167e42752008-01-26 09:13:46 +0000301 // clear this processors user timer bit in config
302 // register
Blue Swirl7204ff92009-08-08 20:08:15 +0000303 s->cputimer_mode &= ~processor;
Blue Swirl97bf4852010-10-31 09:24:14 +0000304 trace_slavio_timer_mem_writel_mode_counter(timer_index);
blueswir167e42752008-01-26 09:13:46 +0000305 }
blueswir1115646b2007-10-07 10:00:55 +0000306 }
blueswir181732d12007-10-06 11:25:43 +0000307 }
Blue Swirl7204ff92009-08-08 20:08:15 +0000308 } else {
Blue Swirl97bf4852010-10-31 09:24:14 +0000309 trace_slavio_timer_mem_writel_mode_invalid();
Blue Swirl7204ff92009-08-08 20:08:15 +0000310 }
blueswir1f930d072007-10-06 11:28:21 +0000311 break;
bellarde80cfcf2004-12-19 23:18:01 +0000312 default:
Blue Swirl97bf4852010-10-31 09:24:14 +0000313 trace_slavio_timer_mem_writel_invalid(addr);
blueswir1f930d072007-10-06 11:28:21 +0000314 break;
bellarde80cfcf2004-12-19 23:18:01 +0000315 }
316}
317
Benoît Caneta3d12d02011-11-15 12:14:02 +0100318static const MemoryRegionOps slavio_timer_mem_ops = {
319 .read = slavio_timer_mem_readl,
320 .write = slavio_timer_mem_writel,
321 .endianness = DEVICE_NATIVE_ENDIAN,
322 .valid = {
323 .min_access_size = 4,
324 .max_access_size = 4,
325 },
bellarde80cfcf2004-12-19 23:18:01 +0000326};
327
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000328static const VMStateDescription vmstate_timer = {
329 .name ="timer",
330 .version_id = 3,
331 .minimum_version_id = 3,
Juan Quintela35d08452014-04-16 16:01:33 +0200332 .fields = (VMStateField[]) {
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000333 VMSTATE_UINT64(limit, CPUTimerState),
334 VMSTATE_UINT32(count, CPUTimerState),
335 VMSTATE_UINT32(counthigh, CPUTimerState),
336 VMSTATE_UINT32(reached, CPUTimerState),
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000337 VMSTATE_UINT32(run , CPUTimerState),
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000338 VMSTATE_PTIMER(timer, CPUTimerState),
339 VMSTATE_END_OF_LIST()
Blue Swirl7204ff92009-08-08 20:08:15 +0000340 }
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000341};
bellarde80cfcf2004-12-19 23:18:01 +0000342
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000343static const VMStateDescription vmstate_slavio_timer = {
344 .name ="slavio_timer",
345 .version_id = 3,
346 .minimum_version_id = 3,
Juan Quintela35d08452014-04-16 16:01:33 +0200347 .fields = (VMStateField[]) {
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000348 VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
349 vmstate_timer, CPUTimerState),
350 VMSTATE_END_OF_LIST()
Blue Swirl7204ff92009-08-08 20:08:15 +0000351 }
Blue Swirlf4b19cd2009-08-31 19:30:18 +0000352};
bellarde80cfcf2004-12-19 23:18:01 +0000353
Blue Swirl0e0bfee2009-10-24 17:35:13 +0000354static void slavio_timer_reset(DeviceState *d)
bellarde80cfcf2004-12-19 23:18:01 +0000355{
Andreas Färberc2754712013-07-27 15:24:22 +0200356 SLAVIO_TIMERState *s = SLAVIO_TIMER(d);
Blue Swirl7204ff92009-08-08 20:08:15 +0000357 unsigned int i;
358 CPUTimerState *curr_timer;
bellarde80cfcf2004-12-19 23:18:01 +0000359
Blue Swirl7204ff92009-08-08 20:08:15 +0000360 for (i = 0; i <= MAX_CPUS; i++) {
361 curr_timer = &s->cputimer[i];
362 curr_timer->limit = 0;
363 curr_timer->count = 0;
364 curr_timer->reached = 0;
Artyom Tarasenko5933e8a2010-08-02 19:58:21 +0200365 if (i <= s->num_cpus) {
Blue Swirl7204ff92009-08-08 20:08:15 +0000366 ptimer_set_limit(curr_timer->timer,
367 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
368 ptimer_run(curr_timer->timer, 0);
Mark Cave-Aylandead4cf02014-02-22 22:54:53 +0000369 curr_timer->run = 1;
Blue Swirl7204ff92009-08-08 20:08:15 +0000370 }
blueswir185e30232007-12-27 20:23:20 +0000371 }
Blue Swirl7204ff92009-08-08 20:08:15 +0000372 s->cputimer_mode = 0;
bellarde80cfcf2004-12-19 23:18:01 +0000373}
374
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200375static int slavio_timer_init1(SysBusDevice *dev)
Blue Swirlc70c59e2009-07-15 08:53:09 +0000376{
Andreas Färberc2754712013-07-27 15:24:22 +0200377 SLAVIO_TIMERState *s = SLAVIO_TIMER(dev);
blueswir18d05ea82007-05-24 19:48:41 +0000378 QEMUBH *bh;
Blue Swirl7204ff92009-08-08 20:08:15 +0000379 unsigned int i;
380 TimerContext *tc;
bellarde80cfcf2004-12-19 23:18:01 +0000381
Blue Swirl7204ff92009-08-08 20:08:15 +0000382 for (i = 0; i <= MAX_CPUS; i++) {
Benoît Caneta3d12d02011-11-15 12:14:02 +0100383 uint64_t size;
384 char timer_name[20];
385
Anthony Liguori7267c092011-08-20 22:09:37 -0500386 tc = g_malloc0(sizeof(TimerContext));
Blue Swirl7204ff92009-08-08 20:08:15 +0000387 tc->s = s;
388 tc->timer_index = i;
Blue Swirlc70c59e2009-07-15 08:53:09 +0000389
Blue Swirl7204ff92009-08-08 20:08:15 +0000390 bh = qemu_bh_new(slavio_timer_irq, tc);
391 s->cputimer[i].timer = ptimer_init(bh);
392 ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
bellarde80cfcf2004-12-19 23:18:01 +0000393
Benoît Caneta3d12d02011-11-15 12:14:02 +0100394 size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
395 snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
Paolo Bonzini853dca12013-06-06 21:25:08 -0400396 memory_region_init_io(&tc->iomem, OBJECT(s), &slavio_timer_mem_ops, tc,
Benoît Caneta3d12d02011-11-15 12:14:02 +0100397 timer_name, size);
Avi Kivity750ecd42011-11-27 11:38:10 +0200398 sysbus_init_mmio(dev, &tc->iomem);
Blue Swirl7204ff92009-08-08 20:08:15 +0000399
400 sysbus_init_irq(dev, &s->cputimer[i].irq);
Blue Swirlc70c59e2009-07-15 08:53:09 +0000401 }
402
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200403 return 0;
blueswir181732d12007-10-06 11:25:43 +0000404}
405
Anthony Liguori999e12b2012-01-24 13:12:29 -0600406static Property slavio_timer_properties[] = {
407 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
408 DEFINE_PROP_END_OF_LIST(),
409};
410
411static void slavio_timer_class_init(ObjectClass *klass, void *data)
412{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600413 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600414 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
415
416 k->init = slavio_timer_init1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600417 dc->reset = slavio_timer_reset;
418 dc->vmsd = &vmstate_slavio_timer;
419 dc->props = slavio_timer_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600420}
421
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100422static const TypeInfo slavio_timer_info = {
Andreas Färberc2754712013-07-27 15:24:22 +0200423 .name = TYPE_SLAVIO_TIMER,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600424 .parent = TYPE_SYS_BUS_DEVICE,
425 .instance_size = sizeof(SLAVIO_TIMERState),
426 .class_init = slavio_timer_class_init,
Blue Swirlc70c59e2009-07-15 08:53:09 +0000427};
428
Andreas Färber83f7d432012-02-09 15:20:55 +0100429static void slavio_timer_register_types(void)
Blue Swirlc70c59e2009-07-15 08:53:09 +0000430{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600431 type_register_static(&slavio_timer_info);
Blue Swirlc70c59e2009-07-15 08:53:09 +0000432}
433
Andreas Färber83f7d432012-02-09 15:20:55 +0100434type_init(slavio_timer_register_types)