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ths83fa1012007-10-08 13:26:33 +00001/*
edgar_igle62b5b12008-03-14 01:04:24 +00002 * QEMU ETRAX Timers
ths83fa1012007-10-08 13:26:33 +00003 *
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010024#include "hw/sysbus.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010025#include "sysemu/sysemu.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010026#include "qemu/timer.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010027#include "hw/ptimer.h"
ths83fa1012007-10-08 13:26:33 +000028
edgar_iglbbaf29c2008-03-01 17:25:33 +000029#define D(x)
30
edgar_iglca87d032008-03-14 01:50:49 +000031#define RW_TMR0_DIV 0x00
32#define R_TMR0_DATA 0x04
33#define RW_TMR0_CTRL 0x08
34#define RW_TMR1_DIV 0x10
35#define R_TMR1_DATA 0x14
36#define RW_TMR1_CTRL 0x18
37#define R_TIME 0x38
38#define RW_WD_CTRL 0x40
edgar_igl54397792008-05-27 21:04:41 +000039#define R_WD_STAT 0x44
edgar_iglca87d032008-03-14 01:50:49 +000040#define RW_INTR_MASK 0x48
41#define RW_ACK_INTR 0x4c
42#define R_INTR 0x50
43#define R_MASKED_INTR 0x54
ths83fa1012007-10-08 13:26:33 +000044
Andreas Färber5880ce52013-07-27 14:34:22 +020045#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
46#define ETRAX_TIMER(obj) \
47 OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
48
Andreas Färber3c9a8a82013-07-27 14:30:31 +020049typedef struct ETRAXTimerState {
Andreas Färber5880ce52013-07-27 14:34:22 +020050 SysBusDevice parent_obj;
51
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +020052 MemoryRegion mmio;
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +020053 qemu_irq irq;
54 qemu_irq nmi;
edgar_iglca87d032008-03-14 01:50:49 +000055
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020056 QEMUBH *bh_t0;
57 QEMUBH *bh_t1;
58 QEMUBH *bh_wd;
59 ptimer_state *ptimer_t0;
60 ptimer_state *ptimer_t1;
61 ptimer_state *ptimer_wd;
edgar_igle62b5b12008-03-14 01:04:24 +000062
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020063 int wd_hits;
edgar_igl5ef98b42008-06-09 23:33:30 +000064
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020065 /* Control registers. */
66 uint32_t rw_tmr0_div;
67 uint32_t r_tmr0_data;
68 uint32_t rw_tmr0_ctrl;
edgar_igl60237222008-05-02 22:32:02 +000069
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020070 uint32_t rw_tmr1_div;
71 uint32_t r_tmr1_data;
72 uint32_t rw_tmr1_ctrl;
edgar_igl60237222008-05-02 22:32:02 +000073
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020074 uint32_t rw_wd_ctrl;
edgar_igl54397792008-05-27 21:04:41 +000075
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020076 uint32_t rw_intr_mask;
77 uint32_t rw_ack_intr;
78 uint32_t r_intr;
79 uint32_t r_masked_intr;
Andreas Färber3c9a8a82013-07-27 14:30:31 +020080} ETRAXTimerState;
ths83fa1012007-10-08 13:26:33 +000081
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +020082static uint64_t
Avi Kivitya8170e52012-10-23 12:30:10 +020083timer_read(void *opaque, hwaddr addr, unsigned int size)
ths83fa1012007-10-08 13:26:33 +000084{
Andreas Färber3c9a8a82013-07-27 14:30:31 +020085 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020086 uint32_t r = 0;
ths83fa1012007-10-08 13:26:33 +000087
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020088 switch (addr) {
89 case R_TMR0_DATA:
90 r = ptimer_get_count(t->ptimer_t0);
91 break;
92 case R_TMR1_DATA:
93 r = ptimer_get_count(t->ptimer_t1);
94 break;
95 case R_TIME:
Alex Blighbc72ad62013-08-21 16:03:08 +010096 r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020097 break;
98 case RW_INTR_MASK:
99 r = t->rw_intr_mask;
100 break;
101 case R_MASKED_INTR:
102 r = t->r_intr & t->rw_intr_mask;
103 break;
104 default:
105 D(printf ("%s %x\n", __func__, addr));
106 break;
107 }
108 return r;
ths83fa1012007-10-08 13:26:33 +0000109}
110
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200111static void update_ctrl(ETRAXTimerState *t, int tnum)
ths83fa1012007-10-08 13:26:33 +0000112{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200113 unsigned int op;
114 unsigned int freq;
115 unsigned int freq_hz;
116 unsigned int div;
117 uint32_t ctrl;
edgar_igl5ef98b42008-06-09 23:33:30 +0000118
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200119 ptimer_state *timer;
ths83fa1012007-10-08 13:26:33 +0000120
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200121 if (tnum == 0) {
122 ctrl = t->rw_tmr0_ctrl;
123 div = t->rw_tmr0_div;
124 timer = t->ptimer_t0;
125 } else {
126 ctrl = t->rw_tmr1_ctrl;
127 div = t->rw_tmr1_div;
128 timer = t->ptimer_t1;
129 }
edgar_igl54397792008-05-27 21:04:41 +0000130
131
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200132 op = ctrl & 3;
133 freq = ctrl >> 2;
134 freq_hz = 32000000;
ths83fa1012007-10-08 13:26:33 +0000135
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200136 switch (freq)
137 {
138 case 0:
139 case 1:
140 D(printf ("extern or disabled timer clock?\n"));
141 break;
142 case 4: freq_hz = 29493000; break;
143 case 5: freq_hz = 32000000; break;
144 case 6: freq_hz = 32768000; break;
145 case 7: freq_hz = 100000000; break;
146 default:
147 abort();
148 break;
149 }
ths83fa1012007-10-08 13:26:33 +0000150
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200151 D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200152 ptimer_set_freq(timer, freq_hz);
153 ptimer_set_limit(timer, div, 0);
ths83fa1012007-10-08 13:26:33 +0000154
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200155 switch (op)
156 {
157 case 0:
158 /* Load. */
159 ptimer_set_limit(timer, div, 1);
160 break;
161 case 1:
162 /* Hold. */
163 ptimer_stop(timer);
164 break;
165 case 2:
166 /* Run. */
167 ptimer_run(timer, 0);
168 break;
169 default:
170 abort();
171 break;
172 }
ths83fa1012007-10-08 13:26:33 +0000173}
174
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200175static void timer_update_irq(ETRAXTimerState *t)
ths83fa1012007-10-08 13:26:33 +0000176{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200177 t->r_intr &= ~(t->rw_ack_intr);
178 t->r_masked_intr = t->r_intr & t->rw_intr_mask;
edgar_igl60237222008-05-02 22:32:02 +0000179
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200180 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200181 qemu_set_irq(t->irq, !!t->r_masked_intr);
ths83fa1012007-10-08 13:26:33 +0000182}
183
edgar_igl54397792008-05-27 21:04:41 +0000184static void timer0_hit(void *opaque)
edgar_igl60237222008-05-02 22:32:02 +0000185{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200186 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200187 t->r_intr |= 1;
188 timer_update_irq(t);
edgar_igl60237222008-05-02 22:32:02 +0000189}
190
edgar_igl54397792008-05-27 21:04:41 +0000191static void timer1_hit(void *opaque)
192{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200193 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200194 t->r_intr |= 2;
195 timer_update_irq(t);
edgar_igl54397792008-05-27 21:04:41 +0000196}
197
198static void watchdog_hit(void *opaque)
199{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200200 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200201 if (t->wd_hits == 0) {
202 /* real hw gives a single tick before reseting but we are
203 a bit friendlier to compensate for our slower execution. */
204 ptimer_set_count(t->ptimer_wd, 10);
205 ptimer_run(t->ptimer_wd, 1);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200206 qemu_irq_raise(t->nmi);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200207 }
208 else
209 qemu_system_reset_request();
edgar_igl5ef98b42008-06-09 23:33:30 +0000210
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200211 t->wd_hits++;
edgar_igl54397792008-05-27 21:04:41 +0000212}
213
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200214static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
edgar_igl54397792008-05-27 21:04:41 +0000215{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200216 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
217 unsigned int wd_key = t->rw_wd_ctrl >> 9;
218 unsigned int wd_cnt = t->rw_wd_ctrl & 511;
219 unsigned int new_key = value >> 9 & ((1 << 7) - 1);
220 unsigned int new_cmd = (value >> 8) & 1;
edgar_igl54397792008-05-27 21:04:41 +0000221
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200222 /* If the watchdog is enabled, they written key must match the
223 complement of the previous. */
224 wd_key = ~wd_key & ((1 << 7) - 1);
edgar_igl54397792008-05-27 21:04:41 +0000225
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200226 if (wd_en && wd_key != new_key)
227 return;
edgar_igl54397792008-05-27 21:04:41 +0000228
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200229 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
230 wd_en, new_key, wd_key, new_cmd, wd_cnt));
edgar_igl54397792008-05-27 21:04:41 +0000231
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200232 if (t->wd_hits)
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200233 qemu_irq_lower(t->nmi);
edgar_igl5ef98b42008-06-09 23:33:30 +0000234
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200235 t->wd_hits = 0;
edgar_igl5ef98b42008-06-09 23:33:30 +0000236
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200237 ptimer_set_freq(t->ptimer_wd, 760);
238 if (wd_cnt == 0)
239 wd_cnt = 256;
240 ptimer_set_count(t->ptimer_wd, wd_cnt);
241 if (new_cmd)
242 ptimer_run(t->ptimer_wd, 1);
243 else
244 ptimer_stop(t->ptimer_wd);
edgar_igl54397792008-05-27 21:04:41 +0000245
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200246 t->rw_wd_ctrl = value;
edgar_igl54397792008-05-27 21:04:41 +0000247}
248
ths83fa1012007-10-08 13:26:33 +0000249static void
Avi Kivitya8170e52012-10-23 12:30:10 +0200250timer_write(void *opaque, hwaddr addr,
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200251 uint64_t val64, unsigned int size)
ths83fa1012007-10-08 13:26:33 +0000252{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200253 ETRAXTimerState *t = opaque;
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200254 uint32_t value = val64;
edgar_iglbbaf29c2008-03-01 17:25:33 +0000255
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200256 switch (addr)
257 {
258 case RW_TMR0_DIV:
259 t->rw_tmr0_div = value;
260 break;
261 case RW_TMR0_CTRL:
262 D(printf ("RW_TMR0_CTRL=%x\n", value));
263 t->rw_tmr0_ctrl = value;
264 update_ctrl(t, 0);
265 break;
266 case RW_TMR1_DIV:
267 t->rw_tmr1_div = value;
268 break;
269 case RW_TMR1_CTRL:
270 D(printf ("RW_TMR1_CTRL=%x\n", value));
271 t->rw_tmr1_ctrl = value;
272 update_ctrl(t, 1);
273 break;
274 case RW_INTR_MASK:
275 D(printf ("RW_INTR_MASK=%x\n", value));
276 t->rw_intr_mask = value;
277 timer_update_irq(t);
278 break;
279 case RW_WD_CTRL:
280 timer_watchdog_update(t, value);
281 break;
282 case RW_ACK_INTR:
283 t->rw_ack_intr = value;
284 timer_update_irq(t);
285 t->rw_ack_intr = 0;
286 break;
287 default:
288 printf ("%s " TARGET_FMT_plx " %x\n",
289 __func__, addr, value);
290 break;
291 }
ths83fa1012007-10-08 13:26:33 +0000292}
293
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200294static const MemoryRegionOps timer_ops = {
295 .read = timer_read,
296 .write = timer_write,
297 .endianness = DEVICE_LITTLE_ENDIAN,
298 .valid = {
299 .min_access_size = 4,
300 .max_access_size = 4
301 }
ths83fa1012007-10-08 13:26:33 +0000302};
303
edgar_igl54397792008-05-27 21:04:41 +0000304static void etraxfs_timer_reset(void *opaque)
305{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200306 ETRAXTimerState *t = opaque;
edgar_igl54397792008-05-27 21:04:41 +0000307
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200308 ptimer_stop(t->ptimer_t0);
309 ptimer_stop(t->ptimer_t1);
310 ptimer_stop(t->ptimer_wd);
311 t->rw_wd_ctrl = 0;
312 t->r_intr = 0;
313 t->rw_intr_mask = 0;
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200314 qemu_irq_lower(t->irq);
edgar_igl54397792008-05-27 21:04:41 +0000315}
316
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200317static int etraxfs_timer_init(SysBusDevice *dev)
ths83fa1012007-10-08 13:26:33 +0000318{
Andreas Färber5880ce52013-07-27 14:34:22 +0200319 ETRAXTimerState *t = ETRAX_TIMER(dev);
ths83fa1012007-10-08 13:26:33 +0000320
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200321 t->bh_t0 = qemu_bh_new(timer0_hit, t);
322 t->bh_t1 = qemu_bh_new(timer1_hit, t);
323 t->bh_wd = qemu_bh_new(watchdog_hit, t);
324 t->ptimer_t0 = ptimer_init(t->bh_t0);
325 t->ptimer_t1 = ptimer_init(t->bh_t1);
326 t->ptimer_wd = ptimer_init(t->bh_wd);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200327
328 sysbus_init_irq(dev, &t->irq);
329 sysbus_init_irq(dev, &t->nmi);
ths83fa1012007-10-08 13:26:33 +0000330
Paolo Bonzini853dca12013-06-06 21:25:08 -0400331 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
332 "etraxfs-timer", 0x5c);
Avi Kivity750ecd42011-11-27 11:38:10 +0200333 sysbus_init_mmio(dev, &t->mmio);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200334 qemu_register_reset(etraxfs_timer_reset, t);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200335 return 0;
ths83fa1012007-10-08 13:26:33 +0000336}
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200337
Anthony Liguori999e12b2012-01-24 13:12:29 -0600338static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
339{
340 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
341
342 sdc->init = etraxfs_timer_init;
343}
344
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100345static const TypeInfo etraxfs_timer_info = {
Andreas Färber5880ce52013-07-27 14:34:22 +0200346 .name = TYPE_ETRAX_FS_TIMER,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600347 .parent = TYPE_SYS_BUS_DEVICE,
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200348 .instance_size = sizeof(ETRAXTimerState),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600349 .class_init = etraxfs_timer_class_init,
Anthony Liguori999e12b2012-01-24 13:12:29 -0600350};
351
Andreas Färber83f7d432012-02-09 15:20:55 +0100352static void etraxfs_timer_register_types(void)
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200353{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600354 type_register_static(&etraxfs_timer_info);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200355}
356
Andreas Färber83f7d432012-02-09 15:20:55 +0100357type_init(etraxfs_timer_register_types)