blob: 1dfa331e6013313eeb7b7e22b1970d9d4ea0b3a0 [file] [log] [blame]
Juan Quintela47d37dd2009-08-31 16:07:15 +02001/*
2 * QEMU PCI VGA Emulator.
3 *
Gerd Hoffmanncc228242012-10-15 08:02:56 +02004 * see docs/specs/standard-vga.txt for virtual hardware specs.
5 *
Juan Quintela47d37dd2009-08-31 16:07:15 +02006 * Copyright (c) 2003 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010026#include "hw/hw.h"
Paolo Bonzini28ecbae2012-11-28 12:06:30 +010027#include "ui/console.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010028#include "hw/pci/pci.h"
Paolo Bonzini47b43a12013-03-18 17:36:02 +010029#include "vga_int.h"
Paolo Bonzini28ecbae2012-11-28 12:06:30 +010030#include "ui/pixel_ops.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010031#include "qemu/timer.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010032#include "hw/loader.h"
Juan Quintela47d37dd2009-08-31 16:07:15 +020033
Gerd Hoffmann803ff052012-10-15 08:02:55 +020034#define PCI_VGA_IOPORT_OFFSET 0x400
35#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
36#define PCI_VGA_BOCHS_OFFSET 0x500
37#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +020038#define PCI_VGA_QEXT_OFFSET 0x600
39#define PCI_VGA_QEXT_SIZE (2 * 4)
Gerd Hoffmann803ff052012-10-15 08:02:55 +020040#define PCI_VGA_MMIO_SIZE 0x1000
41
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +020042#define PCI_VGA_QEXT_REG_SIZE (0 * 4)
43#define PCI_VGA_QEXT_REG_BYTEORDER (1 * 4)
44#define PCI_VGA_QEXT_LITTLE_ENDIAN 0x1e1e1e1e
45#define PCI_VGA_QEXT_BIG_ENDIAN 0xbebebebe
46
Gerd Hoffmann803ff052012-10-15 08:02:55 +020047enum vga_pci_flags {
48 PCI_VGA_FLAG_ENABLE_MMIO = 1,
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +020049 PCI_VGA_FLAG_ENABLE_QEXT = 2,
Gerd Hoffmann803ff052012-10-15 08:02:55 +020050};
51
Juan Quintela47d37dd2009-08-31 16:07:15 +020052typedef struct PCIVGAState {
53 PCIDevice dev;
54 VGACommonState vga;
Gerd Hoffmann803ff052012-10-15 08:02:55 +020055 uint32_t flags;
56 MemoryRegion mmio;
Gerd Hoffmann220869e2015-04-08 09:50:46 +020057 MemoryRegion mrs[3];
Juan Quintela47d37dd2009-08-31 16:07:15 +020058} PCIVGAState;
59
Gonglei176c3242015-05-12 17:27:08 +080060#define TYPE_PCI_VGA "pci-vga"
61#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
62
Juan Quintelaa4f96312009-10-14 15:42:44 +020063static const VMStateDescription vmstate_vga_pci = {
64 .name = "vga",
65 .version_id = 2,
66 .minimum_version_id = 2,
Juan Quintelad49805a2014-04-16 15:32:32 +020067 .fields = (VMStateField[]) {
Juan Quintelaa4f96312009-10-14 15:42:44 +020068 VMSTATE_PCI_DEVICE(dev, PCIVGAState),
69 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
70 VMSTATE_END_OF_LIST()
Juan Quintela47d37dd2009-08-31 16:07:15 +020071 }
Juan Quintelaa4f96312009-10-14 15:42:44 +020072};
Juan Quintela47d37dd2009-08-31 16:07:15 +020073
Avi Kivitya8170e52012-10-23 12:30:10 +020074static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
Gerd Hoffmann803ff052012-10-15 08:02:55 +020075 unsigned size)
76{
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +020077 VGACommonState *s = ptr;
Gerd Hoffmann803ff052012-10-15 08:02:55 +020078 uint64_t ret = 0;
79
80 switch (size) {
81 case 1:
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +020082 ret = vga_ioport_read(s, addr + 0x3c0);
Gerd Hoffmann803ff052012-10-15 08:02:55 +020083 break;
84 case 2:
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +020085 ret = vga_ioport_read(s, addr + 0x3c0);
86 ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
Gerd Hoffmann803ff052012-10-15 08:02:55 +020087 break;
88 }
89 return ret;
90}
91
Avi Kivitya8170e52012-10-23 12:30:10 +020092static void pci_vga_ioport_write(void *ptr, hwaddr addr,
Gerd Hoffmann803ff052012-10-15 08:02:55 +020093 uint64_t val, unsigned size)
94{
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +020095 VGACommonState *s = ptr;
Gerd Hoffmannc96c53b2012-11-12 22:33:21 +010096
Gerd Hoffmann803ff052012-10-15 08:02:55 +020097 switch (size) {
98 case 1:
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +020099 vga_ioport_write(s, addr + 0x3c0, val);
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200100 break;
101 case 2:
102 /*
103 * Update bytes in little endian order. Allows to update
104 * indexed registers with a single word write because the
105 * index byte is updated first.
106 */
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200107 vga_ioport_write(s, addr + 0x3c0, val & 0xff);
108 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200109 break;
110 }
111}
112
113static const MemoryRegionOps pci_vga_ioport_ops = {
114 .read = pci_vga_ioport_read,
115 .write = pci_vga_ioport_write,
116 .valid.min_access_size = 1,
117 .valid.max_access_size = 4,
118 .impl.min_access_size = 1,
119 .impl.max_access_size = 2,
120 .endianness = DEVICE_LITTLE_ENDIAN,
121};
122
Avi Kivitya8170e52012-10-23 12:30:10 +0200123static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200124 unsigned size)
125{
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200126 VGACommonState *s = ptr;
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200127 int index = addr >> 1;
128
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200129 vbe_ioport_write_index(s, 0, index);
130 return vbe_ioport_read_data(s, 0);
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200131}
132
Avi Kivitya8170e52012-10-23 12:30:10 +0200133static void pci_vga_bochs_write(void *ptr, hwaddr addr,
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200134 uint64_t val, unsigned size)
135{
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200136 VGACommonState *s = ptr;
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200137 int index = addr >> 1;
138
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200139 vbe_ioport_write_index(s, 0, index);
140 vbe_ioport_write_data(s, 0, val);
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200141}
142
143static const MemoryRegionOps pci_vga_bochs_ops = {
144 .read = pci_vga_bochs_read,
145 .write = pci_vga_bochs_write,
146 .valid.min_access_size = 1,
147 .valid.max_access_size = 4,
148 .impl.min_access_size = 2,
149 .impl.max_access_size = 2,
150 .endianness = DEVICE_LITTLE_ENDIAN,
151};
152
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200153static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
154{
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200155 VGACommonState *s = ptr;
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200156
157 switch (addr) {
158 case PCI_VGA_QEXT_REG_SIZE:
159 return PCI_VGA_QEXT_SIZE;
160 case PCI_VGA_QEXT_REG_BYTEORDER:
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200161 return s->big_endian_fb ?
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200162 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
163 default:
164 return 0;
165 }
166}
167
168static void pci_vga_qext_write(void *ptr, hwaddr addr,
169 uint64_t val, unsigned size)
170{
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200171 VGACommonState *s = ptr;
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200172
173 switch (addr) {
174 case PCI_VGA_QEXT_REG_BYTEORDER:
175 if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200176 s->big_endian_fb = true;
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200177 }
178 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
Gerd Hoffmanncf45ec62015-04-08 09:09:49 +0200179 s->big_endian_fb = false;
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200180 }
181 break;
182 }
183}
184
David Gibson3c2784f2015-02-10 15:36:15 +1100185static bool vga_get_big_endian_fb(Object *obj, Error **errp)
186{
Gonglei176c3242015-05-12 17:27:08 +0800187 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
David Gibson3c2784f2015-02-10 15:36:15 +1100188
189 return d->vga.big_endian_fb;
190}
191
192static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
193{
Gonglei176c3242015-05-12 17:27:08 +0800194 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
David Gibson3c2784f2015-02-10 15:36:15 +1100195
196 d->vga.big_endian_fb = value;
197}
198
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200199static const MemoryRegionOps pci_vga_qext_ops = {
200 .read = pci_vga_qext_read,
201 .write = pci_vga_qext_write,
202 .valid.min_access_size = 4,
203 .valid.max_access_size = 4,
204 .endianness = DEVICE_LITTLE_ENDIAN,
205};
206
Gerd Hoffmannc5d4dac2014-09-10 14:25:45 +0200207void pci_std_vga_mmio_region_init(VGACommonState *s,
208 MemoryRegion *parent,
209 MemoryRegion *subs,
210 bool qext)
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200211{
212 memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s,
213 "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
214 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
215 &subs[0]);
216
217 memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s,
218 "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
219 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
220 &subs[1]);
221
222 if (qext) {
223 memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s,
224 "qemu extended regs", PCI_VGA_QEXT_SIZE);
225 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
226 &subs[2]);
227 }
228}
229
Markus Armbruster9af21db2015-01-19 15:52:30 +0100230static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
Juan Quintela47d37dd2009-08-31 16:07:15 +0200231{
Gonglei176c3242015-05-12 17:27:08 +0800232 PCIVGAState *d = PCI_VGA(dev);
Gerd Hoffmann0d0302e2012-10-15 08:02:54 +0200233 VGACommonState *s = &d->vga;
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200234 bool qext = false;
Juan Quintela47d37dd2009-08-31 16:07:15 +0200235
Gerd Hoffmann0d0302e2012-10-15 08:02:54 +0200236 /* vga + console init */
Gerd Hoffmanne2bbfc82013-10-11 19:56:59 +0200237 vga_common_init(s, OBJECT(dev), true);
Paolo Bonzini712f0cc2013-06-06 21:21:13 -0400238 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
239 true);
Juan Quintela47d37dd2009-08-31 16:07:15 +0200240
Gerd Hoffmann56437062014-01-24 15:35:21 +0100241 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
Juan Quintela47d37dd2009-08-31 16:07:15 +0200242
Gerd Hoffmann0d0302e2012-10-15 08:02:54 +0200243 /* XXX: VGA_RAM_SIZE must be a power of two */
244 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
Juan Quintela47d37dd2009-08-31 16:07:15 +0200245
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200246 /* mmio bar for vga register access */
247 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400248 memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200249
250 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200251 qext = true;
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200252 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
253 }
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200254 pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200255
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200256 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
257 }
258
Gerd Hoffmann0d0302e2012-10-15 08:02:54 +0200259 if (!dev->rom_bar) {
260 /* compatibility with pc-0.13 and older */
Paolo Bonzini83118322013-06-06 21:21:13 -0400261 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
Gerd Hoffmann0d0302e2012-10-15 08:02:54 +0200262 }
Juan Quintela47d37dd2009-08-31 16:07:15 +0200263}
264
David Gibson3c2784f2015-02-10 15:36:15 +1100265static void pci_std_vga_init(Object *obj)
266{
267 /* Expose framebuffer byteorder via QOM */
268 object_property_add_bool(obj, "big-endian-framebuffer",
269 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
270}
271
Markus Armbruster9af21db2015-01-19 15:52:30 +0100272static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100273{
Gonglei176c3242015-05-12 17:27:08 +0800274 PCIVGAState *d = PCI_VGA(dev);
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100275 VGACommonState *s = &d->vga;
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200276 bool qext = false;
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100277
278 /* vga + console init */
279 vga_common_init(s, OBJECT(dev), false);
280 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
281
282 /* mmio bar */
283 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100284
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200285 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200286 qext = true;
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200287 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
288 }
Gerd Hoffmann220869e2015-04-08 09:50:46 +0200289 pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200290
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100291 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
292 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
David Gibson3c2784f2015-02-10 15:36:15 +1100293}
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100294
David Gibson3c2784f2015-02-10 15:36:15 +1100295static void pci_secondary_vga_init(Object *obj)
296{
297 /* Expose framebuffer byteorder via QOM */
298 object_property_add_bool(obj, "big-endian-framebuffer",
299 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100300}
301
302static void pci_secondary_vga_reset(DeviceState *dev)
303{
Gonglei176c3242015-05-12 17:27:08 +0800304 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100305 vga_common_reset(&d->vga);
306}
307
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +0200308static Property vga_pci_properties[] = {
Gerd Hoffmann9e56edc2012-06-11 10:42:53 +0200309 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
Gerd Hoffmann803ff052012-10-15 08:02:55 +0200310 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200311 DEFINE_PROP_BIT("qemu-extended-regs",
312 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +0200313 DEFINE_PROP_END_OF_LIST(),
314};
315
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100316static Property secondary_pci_properties[] = {
317 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
Gerd Hoffmannb5682aa2014-09-23 12:45:56 +0200318 DEFINE_PROP_BIT("qemu-extended-regs",
319 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100320 DEFINE_PROP_END_OF_LIST(),
321};
322
Gonglei176c3242015-05-12 17:27:08 +0800323static void vga_pci_class_init(ObjectClass *klass, void *data)
324{
325 DeviceClass *dc = DEVICE_CLASS(klass);
326 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
327
328 k->vendor_id = PCI_VENDOR_ID_QEMU;
329 k->device_id = PCI_DEVICE_ID_QEMU_VGA;
330 dc->vmsd = &vmstate_vga_pci;
331 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
332}
333
334static const TypeInfo vga_pci_type_info = {
335 .name = TYPE_PCI_VGA,
336 .parent = TYPE_PCI_DEVICE,
337 .instance_size = sizeof(PCIVGAState),
338 .abstract = true,
339 .class_init = vga_pci_class_init,
340};
341
Anthony Liguori40021f02011-12-04 12:22:06 -0600342static void vga_class_init(ObjectClass *klass, void *data)
343{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600344 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600345 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
Isaku Yamahata32902772011-05-25 10:58:31 +0900346
Markus Armbruster9af21db2015-01-19 15:52:30 +0100347 k->realize = pci_std_vga_realize;
Anthony Liguori40021f02011-12-04 12:22:06 -0600348 k->romfile = "vgabios-stdvga.bin";
Anthony Liguori40021f02011-12-04 12:22:06 -0600349 k->class_id = PCI_CLASS_DISPLAY_VGA;
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +0200350 dc->props = vga_pci_properties;
Igor Mammedov2897ae02014-02-05 16:36:48 +0100351 dc->hotpluggable = false;
Anthony Liguori40021f02011-12-04 12:22:06 -0600352}
353
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100354static void secondary_class_init(ObjectClass *klass, void *data)
355{
356 DeviceClass *dc = DEVICE_CLASS(klass);
357 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
358
Markus Armbruster9af21db2015-01-19 15:52:30 +0100359 k->realize = pci_secondary_vga_realize;
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100360 k->class_id = PCI_CLASS_DISPLAY_OTHER;
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100361 dc->props = secondary_pci_properties;
362 dc->reset = pci_secondary_vga_reset;
363}
364
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100365static const TypeInfo vga_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600366 .name = "VGA",
Gonglei176c3242015-05-12 17:27:08 +0800367 .parent = TYPE_PCI_VGA,
David Gibson3c2784f2015-02-10 15:36:15 +1100368 .instance_init = pci_std_vga_init,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600369 .class_init = vga_class_init,
Juan Quintela47d37dd2009-08-31 16:07:15 +0200370};
371
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100372static const TypeInfo secondary_info = {
373 .name = "secondary-vga",
Gonglei176c3242015-05-12 17:27:08 +0800374 .parent = TYPE_PCI_VGA,
David Gibson3c2784f2015-02-10 15:36:15 +1100375 .instance_init = pci_secondary_vga_init,
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100376 .class_init = secondary_class_init,
377};
378
Andreas Färber83f7d432012-02-09 15:20:55 +0100379static void vga_register_types(void)
Juan Quintela47d37dd2009-08-31 16:07:15 +0200380{
Gonglei176c3242015-05-12 17:27:08 +0800381 type_register_static(&vga_pci_type_info);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600382 type_register_static(&vga_info);
Gerd Hoffmann63e3e242012-11-12 14:29:47 +0100383 type_register_static(&secondary_info);
Juan Quintela47d37dd2009-08-31 16:07:15 +0200384}
Andreas Färber83f7d432012-02-09 15:20:55 +0100385
386type_init(vga_register_types)