Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * IMX31 UARTS |
| 3 | * |
| 4 | * Copyright (c) 2008 OKL |
| 5 | * Originally Written by Hans Jiang |
| 6 | * Copyright (c) 2011 NICTA Pty Ltd. |
Jean-Christophe Dubois | cd0bda2 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 7 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 8 | * |
| 9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 10 | * See the COPYING file in the top-level directory. |
| 11 | * |
| 12 | * This is a `bare-bones' implementation of the IMX series serial ports. |
| 13 | * TODO: |
| 14 | * -- implement FIFOs. The real hardware has 32 word transmit |
| 15 | * and receive FIFOs; we currently use a 1-char buffer |
| 16 | * -- implement DMA |
| 17 | * -- implement BAUD-rate and modem lines, for when the backend |
| 18 | * is a real serial device. |
| 19 | */ |
| 20 | |
Jean-Christophe Dubois | cd0bda2 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 21 | #include "hw/char/imx_serial.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 22 | #include "sysemu/sysemu.h" |
Paolo Bonzini | dccfcd0 | 2013-04-08 16:55:25 +0200 | [diff] [blame] | 23 | #include "sysemu/char.h" |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 24 | |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 25 | #ifndef DEBUG_IMX_UART |
| 26 | #define DEBUG_IMX_UART 0 |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 27 | #endif |
| 28 | |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 29 | #define DPRINTF(fmt, args...) \ |
| 30 | do { \ |
| 31 | if (DEBUG_IMX_UART) { \ |
| 32 | fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ |
| 33 | __func__, ##args); \ |
| 34 | } \ |
| 35 | } while (0) |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 36 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 37 | static const VMStateDescription vmstate_imx_serial = { |
Jean-Christophe Dubois | fa2650a | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 38 | .name = TYPE_IMX_SERIAL, |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 39 | .version_id = 1, |
| 40 | .minimum_version_id = 1, |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 41 | .fields = (VMStateField[]) { |
| 42 | VMSTATE_INT32(readbuff, IMXSerialState), |
| 43 | VMSTATE_UINT32(usr1, IMXSerialState), |
| 44 | VMSTATE_UINT32(usr2, IMXSerialState), |
| 45 | VMSTATE_UINT32(ucr1, IMXSerialState), |
| 46 | VMSTATE_UINT32(uts1, IMXSerialState), |
| 47 | VMSTATE_UINT32(onems, IMXSerialState), |
| 48 | VMSTATE_UINT32(ufcr, IMXSerialState), |
| 49 | VMSTATE_UINT32(ubmr, IMXSerialState), |
| 50 | VMSTATE_UINT32(ubrc, IMXSerialState), |
| 51 | VMSTATE_UINT32(ucr3, IMXSerialState), |
| 52 | VMSTATE_END_OF_LIST() |
| 53 | }, |
| 54 | }; |
| 55 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 56 | static void imx_update(IMXSerialState *s) |
| 57 | { |
| 58 | uint32_t flags; |
| 59 | |
| 60 | flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); |
Guenter Roeck | dc14422 | 2015-08-20 08:52:35 -0700 | [diff] [blame] | 61 | if (s->ucr1 & UCR1_TXMPTYEN) { |
| 62 | flags |= (s->uts1 & UTS1_TXEMPTY); |
| 63 | } else { |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 64 | flags &= ~USR1_TRDY; |
| 65 | } |
| 66 | |
| 67 | qemu_set_irq(s->irq, !!flags); |
| 68 | } |
| 69 | |
| 70 | static void imx_serial_reset(IMXSerialState *s) |
| 71 | { |
| 72 | |
| 73 | s->usr1 = USR1_TRDY | USR1_RXDS; |
| 74 | /* |
| 75 | * Fake attachment of a terminal: assert RTS. |
| 76 | */ |
| 77 | s->usr1 |= USR1_RTSS; |
| 78 | s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; |
| 79 | s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; |
| 80 | s->ucr1 = 0; |
| 81 | s->ucr2 = UCR2_SRST; |
| 82 | s->ucr3 = 0x700; |
| 83 | s->ubmr = 0; |
| 84 | s->ubrc = 4; |
| 85 | s->readbuff = URXD_ERR; |
| 86 | } |
| 87 | |
| 88 | static void imx_serial_reset_at_boot(DeviceState *dev) |
| 89 | { |
Andreas Färber | 8d8e348 | 2013-07-24 22:43:22 +0200 | [diff] [blame] | 90 | IMXSerialState *s = IMX_SERIAL(dev); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 91 | |
| 92 | imx_serial_reset(s); |
| 93 | |
| 94 | /* |
| 95 | * enable the uart on boot, so messages from the linux decompresser |
| 96 | * are visible. On real hardware this is done by the boot rom |
| 97 | * before anything else is loaded. |
| 98 | */ |
| 99 | s->ucr1 = UCR1_UARTEN; |
| 100 | s->ucr2 = UCR2_TXEN; |
| 101 | |
| 102 | } |
| 103 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 104 | static uint64_t imx_serial_read(void *opaque, hwaddr offset, |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 105 | unsigned size) |
| 106 | { |
| 107 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 108 | uint32_t c; |
| 109 | |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 110 | DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); |
| 111 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 112 | switch (offset >> 2) { |
| 113 | case 0x0: /* URXD */ |
| 114 | c = s->readbuff; |
| 115 | if (!(s->uts1 & UTS1_RXEMPTY)) { |
| 116 | /* Character is valid */ |
| 117 | c |= URXD_CHARRDY; |
| 118 | s->usr1 &= ~USR1_RRDY; |
| 119 | s->usr2 &= ~USR2_RDR; |
| 120 | s->uts1 |= UTS1_RXEMPTY; |
| 121 | imx_update(s); |
Jean-Christophe Dubois | f7a6785 | 2015-08-13 11:26:22 +0100 | [diff] [blame] | 122 | if (s->chr) { |
| 123 | qemu_chr_accept_input(s->chr); |
| 124 | } |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 125 | } |
| 126 | return c; |
| 127 | |
| 128 | case 0x20: /* UCR1 */ |
| 129 | return s->ucr1; |
| 130 | |
| 131 | case 0x21: /* UCR2 */ |
| 132 | return s->ucr2; |
| 133 | |
| 134 | case 0x25: /* USR1 */ |
| 135 | return s->usr1; |
| 136 | |
| 137 | case 0x26: /* USR2 */ |
| 138 | return s->usr2; |
| 139 | |
| 140 | case 0x2A: /* BRM Modulator */ |
| 141 | return s->ubmr; |
| 142 | |
| 143 | case 0x2B: /* Baud Rate Count */ |
| 144 | return s->ubrc; |
| 145 | |
| 146 | case 0x2d: /* Test register */ |
| 147 | return s->uts1; |
| 148 | |
| 149 | case 0x24: /* UFCR */ |
| 150 | return s->ufcr; |
| 151 | |
| 152 | case 0x2c: |
| 153 | return s->onems; |
| 154 | |
| 155 | case 0x22: /* UCR3 */ |
| 156 | return s->ucr3; |
| 157 | |
| 158 | case 0x23: /* UCR4 */ |
| 159 | case 0x29: /* BRM Incremental */ |
| 160 | return 0x0; /* TODO */ |
| 161 | |
| 162 | default: |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 163 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 164 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 165 | return 0; |
| 166 | } |
| 167 | } |
| 168 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 169 | static void imx_serial_write(void *opaque, hwaddr offset, |
Jean-Christophe Dubois | fa2650a | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 170 | uint64_t value, unsigned size) |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 171 | { |
| 172 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 173 | unsigned char ch; |
| 174 | |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 175 | DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", |
| 176 | offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV"); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 177 | |
| 178 | switch (offset >> 2) { |
| 179 | case 0x10: /* UTXD */ |
| 180 | ch = value; |
| 181 | if (s->ucr2 & UCR2_TXEN) { |
| 182 | if (s->chr) { |
| 183 | qemu_chr_fe_write(s->chr, &ch, 1); |
| 184 | } |
| 185 | s->usr1 &= ~USR1_TRDY; |
| 186 | imx_update(s); |
| 187 | s->usr1 |= USR1_TRDY; |
| 188 | imx_update(s); |
| 189 | } |
| 190 | break; |
| 191 | |
| 192 | case 0x20: /* UCR1 */ |
| 193 | s->ucr1 = value & 0xffff; |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 194 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 195 | DPRINTF("write(ucr1=%x)\n", (unsigned int)value); |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 196 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 197 | imx_update(s); |
| 198 | break; |
| 199 | |
| 200 | case 0x21: /* UCR2 */ |
| 201 | /* |
| 202 | * Only a few bits in control register 2 are implemented as yet. |
| 203 | * If it's intended to use a real serial device as a back-end, this |
| 204 | * register will have to be implemented more fully. |
| 205 | */ |
| 206 | if (!(value & UCR2_SRST)) { |
| 207 | imx_serial_reset(s); |
| 208 | imx_update(s); |
| 209 | value |= UCR2_SRST; |
| 210 | } |
| 211 | if (value & UCR2_RXEN) { |
| 212 | if (!(s->ucr2 & UCR2_RXEN)) { |
Jean-Christophe Dubois | f7a6785 | 2015-08-13 11:26:22 +0100 | [diff] [blame] | 213 | if (s->chr) { |
| 214 | qemu_chr_accept_input(s->chr); |
| 215 | } |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 216 | } |
| 217 | } |
| 218 | s->ucr2 = value & 0xffff; |
| 219 | break; |
| 220 | |
| 221 | case 0x25: /* USR1 */ |
| 222 | value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | |
Jean-Christophe Dubois | fa2650a | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 223 | USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 224 | s->usr1 &= ~value; |
| 225 | break; |
| 226 | |
| 227 | case 0x26: /* USR2 */ |
Jean-Christophe Dubois | fa2650a | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 228 | /* |
| 229 | * Writing 1 to some bits clears them; all other |
| 230 | * values are ignored |
| 231 | */ |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 232 | value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | |
Jean-Christophe Dubois | fa2650a | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 233 | USR2_RIDELT | USR2_IRINT | USR2_WAKE | |
| 234 | USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 235 | s->usr2 &= ~value; |
| 236 | break; |
| 237 | |
Jean-Christophe Dubois | fa2650a | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 238 | /* |
| 239 | * Linux expects to see what it writes to these registers |
| 240 | * We don't currently alter the baud rate |
| 241 | */ |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 242 | case 0x29: /* UBIR */ |
| 243 | s->ubrc = value & 0xffff; |
| 244 | break; |
| 245 | |
| 246 | case 0x2a: /* UBMR */ |
| 247 | s->ubmr = value & 0xffff; |
| 248 | break; |
| 249 | |
| 250 | case 0x2c: /* One ms reg */ |
| 251 | s->onems = value & 0xffff; |
| 252 | break; |
| 253 | |
| 254 | case 0x24: /* FIFO control register */ |
| 255 | s->ufcr = value & 0xffff; |
| 256 | break; |
| 257 | |
| 258 | case 0x22: /* UCR3 */ |
| 259 | s->ucr3 = value & 0xffff; |
| 260 | break; |
| 261 | |
| 262 | case 0x2d: /* UTS1 */ |
| 263 | case 0x23: /* UCR4 */ |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 264 | qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" |
| 265 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 266 | /* TODO */ |
| 267 | break; |
| 268 | |
| 269 | default: |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 270 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 271 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 272 | } |
| 273 | } |
| 274 | |
| 275 | static int imx_can_receive(void *opaque) |
| 276 | { |
| 277 | IMXSerialState *s = (IMXSerialState *)opaque; |
| 278 | return !(s->usr1 & USR1_RRDY); |
| 279 | } |
| 280 | |
| 281 | static void imx_put_data(void *opaque, uint32_t value) |
| 282 | { |
| 283 | IMXSerialState *s = (IMXSerialState *)opaque; |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 284 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 285 | DPRINTF("received char\n"); |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 286 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 287 | s->usr1 |= USR1_RRDY; |
| 288 | s->usr2 |= USR2_RDR; |
| 289 | s->uts1 &= ~UTS1_RXEMPTY; |
| 290 | s->readbuff = value; |
| 291 | imx_update(s); |
| 292 | } |
| 293 | |
| 294 | static void imx_receive(void *opaque, const uint8_t *buf, int size) |
| 295 | { |
| 296 | imx_put_data(opaque, *buf); |
| 297 | } |
| 298 | |
| 299 | static void imx_event(void *opaque, int event) |
| 300 | { |
| 301 | if (event == CHR_EVENT_BREAK) { |
| 302 | imx_put_data(opaque, URXD_BRK); |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | |
| 307 | static const struct MemoryRegionOps imx_serial_ops = { |
| 308 | .read = imx_serial_read, |
| 309 | .write = imx_serial_write, |
| 310 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 311 | }; |
| 312 | |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 313 | static void imx_serial_realize(DeviceState *dev, Error **errp) |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 314 | { |
Andreas Färber | 8d8e348 | 2013-07-24 22:43:22 +0200 | [diff] [blame] | 315 | IMXSerialState *s = IMX_SERIAL(dev); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 316 | |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 317 | if (s->chr) { |
| 318 | qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, |
| 319 | imx_event, s); |
| 320 | } else { |
Jean-Christophe Dubois | 8ccce77 | 2015-10-25 15:16:06 +0100 | [diff] [blame] | 321 | DPRINTF("No char dev for uart\n"); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 322 | } |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 323 | } |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 324 | |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 325 | static void imx_serial_init(Object *obj) |
| 326 | { |
| 327 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 328 | IMXSerialState *s = IMX_SERIAL(obj); |
| 329 | |
| 330 | memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, |
| 331 | TYPE_IMX_SERIAL, 0x1000); |
| 332 | sysbus_init_mmio(sbd, &s->iomem); |
| 333 | sysbus_init_irq(sbd, &s->irq); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 334 | } |
| 335 | |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 336 | static Property imx_serial_properties[] = { |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 337 | DEFINE_PROP_CHR("chardev", IMXSerialState, chr), |
| 338 | DEFINE_PROP_END_OF_LIST(), |
| 339 | }; |
| 340 | |
| 341 | static void imx_serial_class_init(ObjectClass *klass, void *data) |
| 342 | { |
| 343 | DeviceClass *dc = DEVICE_CLASS(klass); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 344 | |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 345 | dc->realize = imx_serial_realize; |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 346 | dc->vmsd = &vmstate_imx_serial; |
| 347 | dc->reset = imx_serial_reset_at_boot; |
Marcel Apfelbaum | 125ee0e | 2013-07-29 17:17:45 +0300 | [diff] [blame] | 348 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 349 | dc->desc = "i.MX series UART"; |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 350 | dc->props = imx_serial_properties; |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 351 | } |
| 352 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 353 | static const TypeInfo imx_serial_info = { |
Jean-Christophe Dubois | f6c6400 | 2015-08-13 11:26:19 +0100 | [diff] [blame] | 354 | .name = TYPE_IMX_SERIAL, |
| 355 | .parent = TYPE_SYS_BUS_DEVICE, |
| 356 | .instance_size = sizeof(IMXSerialState), |
| 357 | .instance_init = imx_serial_init, |
| 358 | .class_init = imx_serial_class_init, |
Peter Chubb | 40b6f91 | 2012-07-04 10:43:33 +0000 | [diff] [blame] | 359 | }; |
| 360 | |
| 361 | static void imx_serial_register_types(void) |
| 362 | { |
| 363 | type_register_static(&imx_serial_info); |
| 364 | } |
| 365 | |
| 366 | type_init(imx_serial_register_types) |