| Louis Yung-Chieh Lo | bc351d0 | 2011-03-31 13:09:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2010 NVIDIA Corporation |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #ifndef __TEGRA2_SPI_H__ |
| 23 | #define __TEGRA2_SPI_H__ |
| 24 | |
| 25 | // *************************************************************************** |
| 26 | // Hardware BARs |
| 27 | |
| 28 | #define TEGRA2_GPIO_BASE 0x6000D000 |
| 29 | #define TEGRA2_SPI_BASE 0x7000C380 |
| 30 | #define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 0x60006000 |
| 31 | #define NV_ADDRESS_MAP_APB_MISC_BASE 0x70000000 |
| 32 | |
| 33 | // *************************************************************************** |
| 34 | // Clock/reset controller |
| 35 | #define CLK_RST_ENB_H_0_OFFSET 0x14 |
| 36 | #define CLK_RST_ENB_H_0_SPI1 (1 << 11) |
| 37 | |
| 38 | // *************************************************************************** |
| 39 | // GPIO controller |
| 40 | |
| 41 | #define GPIO_OFF(port) (((port / 4) * 128) + ((port % 4) * 4)) |
| 42 | #define GPIO_CNF(port) (gpio_base + GPIO_OFF(port) + 0x00) |
| 43 | #define GPIO_OE(port) (gpio_base + GPIO_OFF(port) + 0x10) |
| 44 | #define GPIO_OUT(port) (gpio_base + GPIO_OFF(port) + 0x20) |
| 45 | #define GPIO_IN(port) (gpio_base + GPIO_OFF(port) + 0x30) |
| 46 | #define GPIO_INT_STA(port) (gpio_base + GPIO_OFF(port) + 0x40) |
| 47 | #define GPIO_INT_ENB(port) (gpio_base + GPIO_OFF(port) + 0x50) |
| 48 | #define GPIO_INT_LVL(port) (gpio_base + GPIO_OFF(port) + 0x60) |
| 49 | #define GPIO_INT_CLR(port) (gpio_base + GPIO_OFF(port) + 0x70) |
| 50 | |
| 51 | #define SPI_CMD_GO (1 << 30) |
| 52 | #define SPI_CMD_ACTIVE_SCLK (1 << 26) |
| 53 | #define SPI_CMD_CK_SDA (1 << 21) |
| 54 | #define SPI_CMD_ACTIVE_SDA (1 << 18) |
| 55 | #define SPI_CMD_CS_POL (1 << 16) |
| 56 | #define SPI_CMD_TXEN (1 << 15) |
| 57 | #define SPI_CMD_RXEN (1 << 14) |
| 58 | #define SPI_CMD_CS_VAL (1 << 13) |
| 59 | #define SPI_CMD_CS_SOFT (1 << 12) |
| 60 | #define SPI_CMD_CS_DELAY (1 << 9) |
| 61 | #define SPI_CMD_CS3_EN (1 << 8) |
| 62 | #define SPI_CMD_CS2_EN (1 << 7) |
| 63 | #define SPI_CMD_CS1_EN (1 << 6) |
| 64 | #define SPI_CMD_CS0_EN (1 << 5) |
| 65 | #define SPI_CMD_BIT_LENGTH (1 << 4) |
| 66 | #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F |
| 67 | |
| 68 | #define SPI_STAT_BSY (1 << 31) |
| 69 | #define SPI_STAT_RDY (1 << 30) |
| 70 | #define SPI_STAT_RXF_FLUSH (1 << 29) |
| 71 | #define SPI_STAT_TXF_FLUSH (1 << 28) |
| 72 | #define SPI_STAT_RXF_UNR (1 << 27) |
| 73 | #define SPI_STAT_TXF_OVF (1 << 26) |
| 74 | #define SPI_STAT_RXF_EMPTY (1 << 25) |
| 75 | #define SPI_STAT_RXF_FULL (1 << 24) |
| 76 | #define SPI_STAT_TXF_EMPTY (1 << 23) |
| 77 | #define SPI_STAT_TXF_FULL (1 << 22) |
| 78 | #define SPI_STAT_SEL_TXRX_N (1 << 16) |
| 79 | #define SPI_STAT_CUR_BLKCNT (1 << 15) |
| 80 | |
| 81 | #endif /* __TEGRA2_SPI_H__ */ |