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uwe0f5a3a22009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
uwe0f5a3a22009-05-13 11:36:06 +000015 */
16
hailfinger324a9cc2010-05-26 01:45:41 +000017#if defined(__i386__) || defined(__x86_64__)
18
uwe0f5a3a22009-05-13 11:36:06 +000019#include <stdlib.h>
uwe0f5a3a22009-05-13 11:36:06 +000020#include "flash.h"
hailfinger428f6852010-07-27 22:41:39 +000021#include "programmer.h"
Patrick Georgib6e26e62017-04-11 20:24:22 +020022#include "hwaccess.h"
uwe0f5a3a22009-05-13 11:36:06 +000023
24#define BIOS_ROM_ADDR 0x04
25#define BIOS_ROM_DATA 0x08
26#define INT_STATUS 0x0e
uweb3a82ef2009-05-16 21:39:19 +000027#define INTERNAL_CONFIG 0x00
uwe0f5a3a22009-05-13 11:36:06 +000028#define SELECT_REG_WINDOW 0x800
29
uwe0f5a3a22009-05-13 11:36:06 +000030#define PCI_VENDOR_ID_3COM 0x10b7
31
Patrick Georgi7c30fa92017-03-28 22:47:12 +020032static uint32_t io_base_addr = 0;
hailfinger1ff33dc2010-07-03 11:02:10 +000033static uint32_t internal_conf;
34static uint16_t id;
uweb3a82ef2009-05-16 21:39:19 +000035
Patrick Georgi8ae16572017-03-09 15:59:25 +010036const struct dev_entry nics_3com[] = {
uwe0f5a3a22009-05-13 11:36:06 +000037 /* 3C90xB */
mkarcher6475d3f2010-02-24 00:04:40 +000038 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
39 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
40 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
41 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
42 {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
43 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
44 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
45 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
uwe0f5a3a22009-05-13 11:36:06 +000046
47 /* 3C905C */
mkarcher6475d3f2010-02-24 00:04:40 +000048 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
uwe0f5a3a22009-05-13 11:36:06 +000049
50 /* 3C980C */
mkarcher6475d3f2010-02-24 00:04:40 +000051 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
uwe0f5a3a22009-05-13 11:36:06 +000052
Patrick Georgi8ddfee92017-03-20 14:54:28 +010053 {0},
uwe0f5a3a22009-05-13 11:36:06 +000054};
55
Souvik Ghoshd75cd672016-06-17 14:21:39 -070056static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
57 chipaddr addr);
58static uint8_t nic3com_chip_readb(const struct flashctx *flash,
59 const chipaddr addr);
Patrick Georgi0a9533a2017-02-03 19:28:38 +010060static const struct par_master par_master_nic3com = {
hailfinger76bb7e92011-11-09 23:40:00 +000061 .chip_readb = nic3com_chip_readb,
62 .chip_readw = fallback_chip_readw,
63 .chip_readl = fallback_chip_readl,
64 .chip_readn = fallback_chip_readn,
65 .chip_writeb = nic3com_chip_writeb,
66 .chip_writew = fallback_chip_writew,
67 .chip_writel = fallback_chip_writel,
68 .chip_writen = fallback_chip_writen,
69};
70
David Hendricks93784b42016-08-09 17:00:38 -070071static int nic3com_shutdown(void *data)
dhendrix0ffc2eb2011-06-14 01:35:36 +000072{
73 /* 3COM 3C90xB cards need a special fixup. */
74 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
75 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
76 /* Select register window 3 and restore the receiver status. */
77 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
78 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
79 }
80
dhendrix0ffc2eb2011-06-14 01:35:36 +000081 return 0;
82}
83
David Hendricksac1d25c2016-08-09 17:00:58 -070084int nic3com_init(void)
uwe0f5a3a22009-05-13 11:36:06 +000085{
Patrick Georgi7c30fa92017-03-28 22:47:12 +020086 struct pci_dev *dev = NULL;
87
Patrick Georgi2a2d67f2017-03-09 10:15:39 +010088 if (rget_io_perms())
89 return 1;
uwe0f5a3a22009-05-13 11:36:06 +000090
Patrick Georgi7c30fa92017-03-28 22:47:12 +020091 dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0);
92 if (!dev)
93 return 1;
94
95 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
96 if (!io_base_addr)
97 return 1;
hailfinger1ef766d2010-07-06 09:55:48 +000098
Patrick Georgid490a172017-03-28 23:03:47 +020099 id = dev->device_id;
uweb3a82ef2009-05-16 21:39:19 +0000100
101 /* 3COM 3C90xB cards need a special fixup. */
102 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
uwed75c4f52009-06-02 16:45:59 +0000103 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
uweb3a82ef2009-05-16 21:39:19 +0000104 /* Select register window 3 and save the receiver status. */
105 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
106 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
107
108 /* Set receiver type to MII for full BIOS ROM access. */
109 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
110 }
uwe0f5a3a22009-05-13 11:36:06 +0000111
112 /*
113 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
114 * cards form a 'register window' into one of multiple (usually 8)
115 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
116 */
117 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
118
dhendrix0ffc2eb2011-06-14 01:35:36 +0000119 if (register_shutdown(nic3com_shutdown, NULL))
120 return 1;
hailfinger76bb7e92011-11-09 23:40:00 +0000121
122 max_rom_decode.parallel = 128 * 1024;
Patrick Georgi0a9533a2017-02-03 19:28:38 +0100123 register_par_master(&par_master_nic3com, BUS_PARALLEL);
hailfinger76bb7e92011-11-09 23:40:00 +0000124
uwe0f5a3a22009-05-13 11:36:06 +0000125 return 0;
126}
127
Patrick Georgie39d6442017-03-22 21:23:35 +0100128static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
129 chipaddr addr)
uwe0f5a3a22009-05-13 11:36:06 +0000130{
hailfinger82719632009-05-16 21:22:56 +0000131 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
uwe0f5a3a22009-05-13 11:36:06 +0000132 OUTB(val, io_base_addr + BIOS_ROM_DATA);
133}
134
Patrick Georgie39d6442017-03-22 21:23:35 +0100135static uint8_t nic3com_chip_readb(const struct flashctx *flash,
136 const chipaddr addr)
uwe0f5a3a22009-05-13 11:36:06 +0000137{
hailfinger82719632009-05-16 21:22:56 +0000138 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
uwe4475e902009-05-19 14:14:21 +0000139 return INB(io_base_addr + BIOS_ROM_DATA);
uwe0f5a3a22009-05-13 11:36:06 +0000140}
hailfinger324a9cc2010-05-26 01:45:41 +0000141
142#else
143#error PCI port I/O access is not supported on this architecture yet.
144#endif