blob: 489c9c6f315f23238da1995cea8ceb6a5ff93fed [file] [log] [blame]
uwea3a82c92009-05-15 17:02:34 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
hailfingerbf923c32011-02-15 22:44:27 +00005 * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger
uwea3a82c92009-05-15 17:02:34 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
uwea3a82c92009-05-15 17:02:34 +000017 */
18
19#include <stdlib.h>
20#include <string.h>
uwea3a82c92009-05-15 17:02:34 +000021#include "flash.h"
hailfinger428f6852010-07-27 22:41:39 +000022#include "programmer.h"
uwea3a82c92009-05-15 17:02:34 +000023
uwea3a82c92009-05-15 17:02:34 +000024struct pci_access *pacc;
uwea3a82c92009-05-15 17:02:34 +000025
hailfingerbf923c32011-02-15 22:44:27 +000026enum pci_bartype {
27 TYPE_MEMBAR,
28 TYPE_IOBAR,
29 TYPE_ROMBAR,
30 TYPE_UNKNOWN
31};
32
Patrick Georgif776a442017-03-28 21:34:33 +020033uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
uwea3a82c92009-05-15 17:02:34 +000034{
hailfingerbf923c32011-02-15 22:44:27 +000035 uint64_t addr;
36 uint32_t upperaddr;
37 uint8_t headertype;
38 uint16_t supported_cycles;
39 enum pci_bartype bartype = TYPE_UNKNOWN;
uwea3a82c92009-05-15 17:02:34 +000040
Patrick Georgif776a442017-03-28 21:34:33 +020041
42 headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f;
43 msg_pspew("PCI header type 0x%02x\n", headertype);
44
45 /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */
46 addr = pci_read_long(dev, bar);
47
48 /* Sanity checks. */
49 switch (headertype) {
50 case PCI_HEADER_TYPE_NORMAL:
51 switch (bar) {
52 case PCI_BASE_ADDRESS_0:
53 case PCI_BASE_ADDRESS_1:
54 case PCI_BASE_ADDRESS_2:
55 case PCI_BASE_ADDRESS_3:
56 case PCI_BASE_ADDRESS_4:
57 case PCI_BASE_ADDRESS_5:
58 if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
59 bartype = TYPE_IOBAR;
60 else
61 bartype = TYPE_MEMBAR;
62 break;
63 case PCI_ROM_ADDRESS:
64 bartype = TYPE_ROMBAR;
65 break;
66 }
67 break;
68 case PCI_HEADER_TYPE_BRIDGE:
69 switch (bar) {
70 case PCI_BASE_ADDRESS_0:
71 case PCI_BASE_ADDRESS_1:
72 if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
73 bartype = TYPE_IOBAR;
74 else
75 bartype = TYPE_MEMBAR;
76 break;
77 case PCI_ROM_ADDRESS1:
78 bartype = TYPE_ROMBAR;
79 break;
80 }
81 break;
82 case PCI_HEADER_TYPE_CARDBUS:
83 break;
84 default:
85 msg_perr("Unknown PCI header type 0x%02x, BAR type cannot be determined reliably.\n",
86 headertype);
87 break;
88 }
89
90 supported_cycles = pci_read_word(dev, PCI_COMMAND);
91
92 msg_pdbg("Requested BAR is of type ");
93 switch (bartype) {
94 case TYPE_MEMBAR:
95 msg_pdbg("MEM");
96 if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
97 msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
98 /* TODO: Abort here? */
99 }
100 msg_pdbg(", %sbit, %sprefetchable\n",
101 ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"),
102 (addr & 0x8) ? "" : "not ");
103 if ((addr & 0x6) == 0x4) {
104 /* The spec says that a 64-bit register consumes
105 * two subsequent dword locations.
106 */
107 upperaddr = pci_read_long(dev, bar + 4);
108 if (upperaddr != 0x00000000) {
109 /* Fun! A real 64-bit resource. */
110 if (sizeof(uintptr_t) != sizeof(uint64_t)) {
111 msg_perr("BAR unreachable!");
112 /* TODO: Really abort here? If multiple PCI devices match,
113 * we might never tell the user about the other devices.
114 */
115 return 0;
116 }
117 addr |= (uint64_t)upperaddr << 32;
118 }
119 }
120 addr &= PCI_BASE_ADDRESS_MEM_MASK;
121 break;
122 case TYPE_IOBAR:
123 msg_pdbg("I/O\n");
124#if __FLASHROM_HAVE_OUTB__
125 if (!(supported_cycles & PCI_COMMAND_IO)) {
126 msg_perr("I/O BAR access requested, but device has I/O space accesses disabled.\n");
127 /* TODO: Abort here? */
128 }
129#else
130 msg_perr("I/O BAR access requested, but flashrom does not support I/O BAR access on this "
131 "platform (yet).\n");
132#endif
133 addr &= PCI_BASE_ADDRESS_IO_MASK;
134 break;
135 case TYPE_ROMBAR:
136 msg_pdbg("ROM\n");
137 /* Not sure if this check is needed. */
138 if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
139 msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
140 /* TODO: Abort here? */
141 }
142 addr &= PCI_ROM_ADDRESS_MASK;
143 break;
144 case TYPE_UNKNOWN:
145 msg_perr("BAR type unknown, please report a bug at flashrom@flashrom.org\n");
146 }
147
148 return (uintptr_t)addr;
149}
150
151uintptr_t pcidev_validate(struct pci_dev *dev, int bar,
152 const struct dev_entry *devs)
153{
154 int i;
155
uwea3a82c92009-05-15 17:02:34 +0000156 for (i = 0; devs[i].device_name != NULL; i++) {
157 if (dev->device_id != devs[i].device_id)
158 continue;
159
hailfingerbf923c32011-02-15 22:44:27 +0000160 msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n",
161 devs[i].vendor_name, devs[i].device_name,
162 dev->vendor_id, dev->device_id, dev->bus, dev->dev,
163 dev->func);
164
mkarcher6475d3f2010-02-24 00:04:40 +0000165 if (devs[i].status == NT) {
snelsone42c3802010-05-07 20:09:04 +0000166 msg_pinfo("===\nThis PCI device is UNTESTED. Please "
hailfinger5bae2332010-10-08 11:03:02 +0000167 "report the 'flashrom -p xxxx' output \n"
168 "to flashrom@flashrom.org if it works "
169 "for you. Please add the name of your\n"
170 "PCI device to the subject. Thank you for "
171 "your help!\n===\n");
uwea3a82c92009-05-15 17:02:34 +0000172 }
173
Patrick Georgif776a442017-03-28 21:34:33 +0200174 return pcidev_readbar(dev, bar);
uwea3a82c92009-05-15 17:02:34 +0000175 }
176
177 return 0;
178}
179
Patrick Georgifc8e5d92017-03-21 16:49:15 +0100180static int pcidev_shutdown(void *data)
181{
182 if (pacc == NULL) {
183 msg_perr("%s: Tried to cleanup an invalid PCI context!\n"
184 "Please report a bug at flashrom@flashrom.org\n", __func__);
185 return 1;
186 }
187 pci_cleanup(pacc);
188 return 0;
189}
190
191int pci_init_common(void)
192{
193 if (pacc != NULL) {
194 msg_perr("%s: Tried to allocate a new PCI context, but there is still an old one!\n"
195 "Please report a bug at flashrom@flashrom.org\n", __func__);
196 return 1;
197 }
198 pacc = pci_alloc(); /* Get the pci_access structure */
199 pci_init(pacc); /* Initialize the PCI library */
200 if (register_shutdown(pcidev_shutdown, NULL))
201 return 1;
202 pci_scan_bus(pacc); /* We want to get the list of devices */
203 return 0;
204}
205
Patrick Georgi7c30fa92017-03-28 22:47:12 +0200206struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar)
uwea3a82c92009-05-15 17:02:34 +0000207{
208 struct pci_dev *dev;
hailfinger1ff33dc2010-07-03 11:02:10 +0000209 struct pci_filter filter;
hailfinger1ef766d2010-07-06 09:55:48 +0000210 char *pcidev_bdf;
uwea3a82c92009-05-15 17:02:34 +0000211 char *msg = NULL;
212 int found = 0;
Patrick Georgi7c30fa92017-03-28 22:47:12 +0200213 uintptr_t addr = 0;
uwea3a82c92009-05-15 17:02:34 +0000214
Patrick Georgifc8e5d92017-03-21 16:49:15 +0100215 if (pci_init_common() != 0)
Patrick Georgi7c30fa92017-03-28 22:47:12 +0200216 return NULL;
uwea3a82c92009-05-15 17:02:34 +0000217 pci_filter_init(pacc, &filter);
218
hailfinger0d703d42011-03-07 01:08:09 +0000219 /* Filter by bb:dd.f (if supplied by the user). */
hailfingerddeb4ac2010-07-08 10:13:37 +0000220 pcidev_bdf = extract_programmer_param("pci");
uwea3a82c92009-05-15 17:02:34 +0000221 if (pcidev_bdf != NULL) {
222 if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) {
snelsone42c3802010-05-07 20:09:04 +0000223 msg_perr("Error: %s\n", msg);
uwea3a82c92009-05-15 17:02:34 +0000224 exit(1);
225 }
226 }
hailfinger1ef766d2010-07-06 09:55:48 +0000227 free(pcidev_bdf);
uwea3a82c92009-05-15 17:02:34 +0000228
229 for (dev = pacc->devices; dev; dev = dev->next) {
230 if (pci_filter_match(&filter, dev)) {
hailfinger0d703d42011-03-07 01:08:09 +0000231 /* FIXME: We should count all matching devices, not
232 * just those with a valid BAR.
233 */
uwee2f95ef2009-09-02 23:00:46 +0000234 if ((addr = pcidev_validate(dev, bar, devs)) != 0) {
uwea3a82c92009-05-15 17:02:34 +0000235 found++;
uweb3a82ef2009-05-16 21:39:19 +0000236 }
uwea3a82c92009-05-15 17:02:34 +0000237 }
238 }
239
240 /* Only continue if exactly one supported PCI dev has been found. */
241 if (found == 0) {
snelsone42c3802010-05-07 20:09:04 +0000242 msg_perr("Error: No supported PCI device found.\n");
uwea3a82c92009-05-15 17:02:34 +0000243 exit(1);
244 } else if (found > 1) {
Patrick Georgi2f83ace2017-03-22 21:23:35 +0100245 msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f' \n"
246 "to explicitly select the card with the given BDF (PCI bus, device, function).\n");
uwea3a82c92009-05-15 17:02:34 +0000247 exit(1);
248 }
249
Patrick Georgid490a172017-03-28 23:03:47 +0200250 return dev;
uwea3a82c92009-05-15 17:02:34 +0000251}
252
Patrick Georgi8ae16572017-03-09 15:59:25 +0100253void print_supported_pcidevs(const struct dev_entry *devs)
uwea3a82c92009-05-15 17:02:34 +0000254{
255 int i;
256
hailfingerf79d1712010-10-06 23:48:34 +0000257 msg_pinfo("PCI devices:\n");
uwea3a82c92009-05-15 17:02:34 +0000258 for (i = 0; devs[i].vendor_name != NULL; i++) {
hailfinger495bc2e2010-10-07 22:21:45 +0000259 msg_pinfo("%s %s [%04x:%04x]%s\n", devs[i].vendor_name,
uwe8d342eb2011-07-28 08:13:25 +0000260 devs[i].device_name, devs[i].vendor_id,
261 devs[i].device_id,
262 (devs[i].status == NT) ? " (untested)" : "");
uwea3a82c92009-05-15 17:02:34 +0000263 }
264}
hailfingerf31cbdc2010-11-10 15:25:18 +0000265
266enum pci_write_type {
267 pci_write_type_byte,
268 pci_write_type_word,
269 pci_write_type_long,
270};
271
272struct undo_pci_write_data {
273 struct pci_dev dev;
274 int reg;
275 enum pci_write_type type;
276 union {
277 uint8_t bytedata;
278 uint16_t worddata;
279 uint32_t longdata;
280 };
281};
282
David Hendricks93784b42016-08-09 17:00:38 -0700283int undo_pci_write(void *p)
hailfingerf31cbdc2010-11-10 15:25:18 +0000284{
285 struct undo_pci_write_data *data = p;
286 msg_pdbg("Restoring PCI config space for %02x:%02x:%01x reg 0x%02x\n",
287 data->dev.bus, data->dev.dev, data->dev.func, data->reg);
288 switch (data->type) {
289 case pci_write_type_byte:
290 pci_write_byte(&data->dev, data->reg, data->bytedata);
291 break;
292 case pci_write_type_word:
293 pci_write_word(&data->dev, data->reg, data->worddata);
294 break;
295 case pci_write_type_long:
296 pci_write_long(&data->dev, data->reg, data->longdata);
297 break;
298 }
299 /* p was allocated in register_undo_pci_write. */
300 free(p);
dhendrix0ffc2eb2011-06-14 01:35:36 +0000301 return 0;
hailfingerf31cbdc2010-11-10 15:25:18 +0000302}
303
304#define register_undo_pci_write(a, b, c) \
305{ \
306 struct undo_pci_write_data *undo_pci_write_data; \
307 undo_pci_write_data = malloc(sizeof(struct undo_pci_write_data)); \
stefanctd611e8f2011-07-12 22:35:21 +0000308 if (!undo_pci_write_data) { \
309 msg_gerr("Out of memory!\n"); \
310 exit(1); \
311 } \
hailfingerf31cbdc2010-11-10 15:25:18 +0000312 undo_pci_write_data->dev = *a; \
313 undo_pci_write_data->reg = b; \
314 undo_pci_write_data->type = pci_write_type_##c; \
315 undo_pci_write_data->c##data = pci_read_##c(dev, reg); \
316 register_shutdown(undo_pci_write, undo_pci_write_data); \
317}
318
319#define register_undo_pci_write_byte(a, b) register_undo_pci_write(a, b, byte)
320#define register_undo_pci_write_word(a, b) register_undo_pci_write(a, b, word)
321#define register_undo_pci_write_long(a, b) register_undo_pci_write(a, b, long)
322
323int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data)
324{
325 register_undo_pci_write_byte(dev, reg);
326 return pci_write_byte(dev, reg, data);
327}
328
329int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data)
330{
331 register_undo_pci_write_word(dev, reg);
332 return pci_write_word(dev, reg, data);
333}
334
335int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data)
336{
337 register_undo_pci_write_long(dev, reg);
338 return pci_write_long(dev, reg, data);
339}