stepan | d4b1375 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger |
stepan | dbd3af1 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
stepan | d4b1375 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
stepan | d4b1375 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | /* |
| 19 | * Contains the generic SPI framework |
| 20 | */ |
| 21 | |
oxygene | 70aa650 | 2011-03-08 07:17:44 +0000 | [diff] [blame] | 22 | #include <strings.h> |
hailfinger | 132df7b | 2010-09-15 00:13:02 +0000 | [diff] [blame] | 23 | #include <string.h> |
stepan | d4b1375 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 24 | #include "flash.h" |
hailfinger | 66966da | 2009-06-15 14:14:48 +0000 | [diff] [blame] | 25 | #include "flashchips.h" |
snelson | 8913d08 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 26 | #include "chipdrivers.h" |
hailfinger | 428f685 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 27 | #include "programmer.h" |
hailfinger | 7803156 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 28 | #include "spi.h" |
stepan | d4b1375 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 29 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 30 | int spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, |
uwe | fa98ca1 | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 31 | const unsigned char *writearr, unsigned char *readarr) |
hailfinger | 35cc816 | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 32 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 33 | if (!flash->mst->spi.command) { |
Duncan Laurie | 870d8af | 2019-01-09 18:05:23 -0800 | [diff] [blame] | 34 | msg_pdbg("%s called, but SPI is unsupported on this " |
David Hendricks | ac1d25c | 2016-08-09 17:00:58 -0700 | [diff] [blame] | 35 | "hardware. Please report a bug at " |
| 36 | "flashrom@flashrom.org\n", __func__); |
| 37 | return 1; |
| 38 | } |
| 39 | |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 40 | return flash->mst->spi.command(flash, writecnt, readcnt, |
David Hendricks | ac1d25c | 2016-08-09 17:00:58 -0700 | [diff] [blame] | 41 | writearr, readarr); |
hailfinger | 35cc816 | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 42 | } |
| 43 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 44 | int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) |
hailfinger | 68002c2 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 45 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 46 | if (!flash->mst->spi.multicommand) { |
Duncan Laurie | 870d8af | 2019-01-09 18:05:23 -0800 | [diff] [blame] | 47 | msg_pdbg("%s called, but SPI is unsupported on this " |
David Hendricks | ac1d25c | 2016-08-09 17:00:58 -0700 | [diff] [blame] | 48 | "hardware. Please report a bug at " |
| 49 | "flashrom@flashrom.org\n", __func__); |
| 50 | return 1; |
| 51 | } |
| 52 | |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 53 | return flash->mst->spi.multicommand(flash, cmds); |
hailfinger | 948b81f | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 56 | int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, |
hailfinger | 948b81f | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 57 | const unsigned char *writearr, unsigned char *readarr) |
| 58 | { |
| 59 | struct spi_command cmd[] = { |
| 60 | { |
| 61 | .writecnt = writecnt, |
| 62 | .readcnt = readcnt, |
| 63 | .writearr = writearr, |
| 64 | .readarr = readarr, |
| 65 | }, { |
| 66 | .writecnt = 0, |
| 67 | .writearr = NULL, |
| 68 | .readcnt = 0, |
| 69 | .readarr = NULL, |
| 70 | }}; |
| 71 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 72 | return spi_send_multicommand(flash, cmd); |
hailfinger | 948b81f | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 73 | } |
| 74 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 75 | int default_spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) |
hailfinger | 948b81f | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 76 | { |
| 77 | int result = 0; |
hailfinger | bb09211 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 78 | for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 79 | result = spi_send_command(flash, cmds->writecnt, cmds->readcnt, |
hailfinger | bb09211 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 80 | cmds->writearr, cmds->readarr); |
hailfinger | 948b81f | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 81 | } |
| 82 | return result; |
hailfinger | 68002c2 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 85 | int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) |
mkarcher | 8fb5759 | 2011-05-11 17:07:02 +0000 | [diff] [blame] | 86 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 87 | unsigned int max_data = flash->mst->spi.max_data_read; |
David Hendricks | 1ed1d35 | 2011-11-23 17:54:37 -0800 | [diff] [blame] | 88 | int rc; |
mkarcher | 8fb5759 | 2011-05-11 17:07:02 +0000 | [diff] [blame] | 89 | if (max_data == MAX_DATA_UNSPECIFIED) { |
| 90 | msg_perr("%s called, but SPI read chunk size not defined " |
| 91 | "on this hardware. Please report a bug at " |
| 92 | "flashrom@flashrom.org\n", __func__); |
| 93 | return 1; |
| 94 | } |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 95 | if (flash->chip->feature_bits & FEATURE_UNBOUND_READ) |
Duncan Laurie | 06ffd52 | 2015-10-26 12:56:08 -0700 | [diff] [blame] | 96 | rc = spi_read_unbound(flash, buf, start, len, max_data); |
| 97 | else |
| 98 | rc = spi_read_chunked(flash, buf, start, len, max_data); |
David Hendricks | 1ed1d35 | 2011-11-23 17:54:37 -0800 | [diff] [blame] | 99 | /* translate SPI-specific access denied error to generic error */ |
| 100 | if (rc == SPI_ACCESS_DENIED) |
| 101 | rc = ACCESS_DENIED; |
| 102 | return rc; |
mkarcher | 8fb5759 | 2011-05-11 17:07:02 +0000 | [diff] [blame] | 103 | } |
| 104 | |
Patrick Georgi | ab8353e | 2017-02-03 18:32:01 +0100 | [diff] [blame] | 105 | int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) |
mkarcher | 8fb5759 | 2011-05-11 17:07:02 +0000 | [diff] [blame] | 106 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 107 | unsigned int max_data = flash->mst->spi.max_data_write; |
David Hendricks | 1ed1d35 | 2011-11-23 17:54:37 -0800 | [diff] [blame] | 108 | int rc; |
mkarcher | 8fb5759 | 2011-05-11 17:07:02 +0000 | [diff] [blame] | 109 | if (max_data == MAX_DATA_UNSPECIFIED) { |
| 110 | msg_perr("%s called, but SPI write chunk size not defined " |
| 111 | "on this hardware. Please report a bug at " |
| 112 | "flashrom@flashrom.org\n", __func__); |
| 113 | return 1; |
| 114 | } |
David Hendricks | 1ed1d35 | 2011-11-23 17:54:37 -0800 | [diff] [blame] | 115 | rc = spi_write_chunked(flash, buf, start, len, max_data); |
| 116 | /* translate SPI-specific access denied error to generic error */ |
| 117 | if (rc == SPI_ACCESS_DENIED) |
| 118 | rc = ACCESS_DENIED; |
| 119 | return rc; |
mkarcher | 8fb5759 | 2011-05-11 17:07:02 +0000 | [diff] [blame] | 120 | } |
| 121 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 122 | int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) |
hailfinger | b8f7e88 | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 123 | { |
stefanct | c5eb8a9 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 124 | unsigned int addrbase = 0; |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 125 | if (!flash->mst->spi.read) { |
David Hendricks | ac1d25c | 2016-08-09 17:00:58 -0700 | [diff] [blame] | 126 | msg_perr("%s called, but SPI read is unsupported on this " |
| 127 | "hardware. Please report a bug at " |
| 128 | "flashrom@flashrom.org\n", __func__); |
| 129 | return 1; |
| 130 | } |
| 131 | |
hailfinger | 132df7b | 2010-09-15 00:13:02 +0000 | [diff] [blame] | 132 | /* Check if the chip fits between lowest valid and highest possible |
| 133 | * address. Highest possible address with the current SPI implementation |
| 134 | * means 0xffffff, the highest unsigned 24bit number. |
| 135 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 136 | addrbase = spi_get_valid_read_addr(flash); |
Boris Baykov | 1a2f532 | 2016-06-11 18:29:00 +0200 | [diff] [blame] | 137 | /* Show flash chip size warning if flash chip doesn't support |
| 138 | 4-Bytes Addressing mode and last address excedes 24 bits */ |
Edward O'Callaghan | 9713aa6 | 2019-07-18 18:28:57 +1000 | [diff] [blame] | 139 | if (!(flash->chip->feature_bits & FEATURE_4BA_ENTER_WREN) && |
Boris Baykov | 1a2f532 | 2016-06-11 18:29:00 +0200 | [diff] [blame] | 140 | addrbase + flash->chip->total_size * 1024 > (1 << 24)) { |
hailfinger | 132df7b | 2010-09-15 00:13:02 +0000 | [diff] [blame] | 141 | msg_perr("Flash chip size exceeds the allowed access window. "); |
| 142 | msg_perr("Read will probably fail.\n"); |
| 143 | /* Try to get the best alignment subject to constraints. */ |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 144 | addrbase = (1 << 24) - flash->chip->total_size * 1024; |
hailfinger | 132df7b | 2010-09-15 00:13:02 +0000 | [diff] [blame] | 145 | } |
| 146 | /* Check if alignment is native (at least the largest power of two which |
| 147 | * is a factor of the mapped size of the chip). |
| 148 | */ |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 149 | if (ffs(flash->chip->total_size * 1024) > (ffs(addrbase) ? : 33)) { |
hailfinger | 132df7b | 2010-09-15 00:13:02 +0000 | [diff] [blame] | 150 | msg_perr("Flash chip is not aligned natively in the allowed " |
| 151 | "access window.\n"); |
| 152 | msg_perr("Read will probably return garbage.\n"); |
| 153 | } |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 154 | return flash->mst->spi.read(flash, buf, addrbase + start, len); |
hailfinger | b8f7e88 | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 155 | } |
| 156 | |
hailfinger | ed063f5 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 157 | /* |
hailfinger | ed063f5 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 158 | * Program chip using page (256 bytes) programming. |
| 159 | * Some SPI masters can't do this, they use single byte programming instead. |
hailfinger | c7d06c6 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 160 | * The redirect to single byte programming is achieved by setting |
| 161 | * .write_256 = spi_chip_write_1 |
hailfinger | ed063f5 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 162 | */ |
hailfinger | c7d06c6 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 163 | /* real chunksize is up to 256, logical chunksize is 256 */ |
Patrick Georgi | ab8353e | 2017-02-03 18:32:01 +0100 | [diff] [blame] | 164 | int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) |
hailfinger | 2c361e4 | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 165 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 166 | if (!flash->mst->spi.write_256) { |
David Hendricks | ac1d25c | 2016-08-09 17:00:58 -0700 | [diff] [blame] | 167 | msg_perr("%s called, but SPI page write is unsupported on this " |
| 168 | "hardware. Please report a bug at " |
| 169 | "flashrom@flashrom.org\n", __func__); |
| 170 | return 1; |
| 171 | } |
| 172 | |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 173 | return flash->mst->spi.write_256(flash, buf, start, len); |
hailfinger | c7d06c6 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 174 | } |
| 175 | |
hailfinger | b767c12 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 176 | /* |
| 177 | * Get the lowest allowed address for read accesses. This often happens to |
| 178 | * be the lowest allowed address for all commands which take an address. |
| 179 | * This is a programmer limitation. |
| 180 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 181 | uint32_t spi_get_valid_read_addr(struct flashctx *flash) |
hailfinger | 54c1466 | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 182 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 183 | switch (flash->mst->spi.type) { |
hailfinger | 90c7d54 | 2010-05-31 15:27:27 +0000 | [diff] [blame] | 184 | #if CONFIG_INTERNAL == 1 |
hailfinger | b767c12 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 185 | #if defined(__i386__) || defined(__x86_64__) |
| 186 | case SPI_CONTROLLER_ICH7: |
| 187 | /* Return BBAR for ICH chipsets. */ |
| 188 | return ichspi_bbar; |
| 189 | #endif |
| 190 | #endif |
| 191 | default: |
| 192 | return 0; |
| 193 | } |
hailfinger | 54c1466 | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 194 | } |
mkarcher | d264e9e | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 195 | |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 196 | int register_spi_master(const struct spi_master *mst) |
mkarcher | d264e9e | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 197 | { |
Edward O'Callaghan | bcae375 | 2018-12-19 13:11:57 +1100 | [diff] [blame] | 198 | struct registered_master rmst; |
| 199 | |
| 200 | if (!mst->write_256 || !mst->read || !mst->command || |
| 201 | !mst->multicommand || |
| 202 | ((mst->command == default_spi_send_command) && |
| 203 | (mst->multicommand == default_spi_send_multicommand))) { |
| 204 | msg_perr("%s called with incomplete master definition. " |
| 205 | "Please report a bug at flashrom@flashrom.org\n", __func__); |
| 206 | return ERROR_FLASHROM_BUG; |
| 207 | } |
| 208 | |
| 209 | rmst.buses_supported = BUS_SPI; |
| 210 | rmst.spi = *mst; |
| 211 | |
| 212 | return register_master(&rmst); |
David Hendricks | 9104083 | 2011-07-08 20:01:09 -0700 | [diff] [blame] | 213 | } |