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hailfinger935365d2011-02-04 21:37:59 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010,2011 Carl-Daniel Hailfinger
5 * Written by Carl-Daniel Hailfinger for Angelbird Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/* Datasheets are not public (yet?) */
hailfingera49e9c12011-07-25 22:07:05 +000022#if defined(__i386__) || defined(__x86_64__)
hailfinger935365d2011-02-04 21:37:59 +000023
24#include <stdlib.h>
25#include "flash.h"
26#include "programmer.h"
27
28uint8_t *mv_bar;
29uint16_t mv_iobar;
30
31const struct pcidev_status satas_mv[] = {
32 /* 88SX6041 and 88SX6042 are the same according to the datasheet. */
33 {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
34
35 {},
36};
37
38#define NVRAM_PARAM 0x1045c
39#define FLASH_PARAM 0x1046c
40#define EXPANSION_ROM_BAR_CONTROL 0x00d2c
41#define PCI_BAR2_CONTROL 0x00c08
42#define GPIO_PORT_CONTROL 0x104f0
43
Souvik Ghoshd75cd672016-06-17 14:21:39 -070044static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
45 chipaddr addr);
46static uint8_t satamv_chip_readb(const struct flashctx *flash,
47 const chipaddr addr);
48
hailfinger76bb7e92011-11-09 23:40:00 +000049static const struct par_programmer par_programmer_satamv = {
50 .chip_readb = satamv_chip_readb,
51 .chip_readw = fallback_chip_readw,
52 .chip_readl = fallback_chip_readl,
53 .chip_readn = fallback_chip_readn,
54 .chip_writeb = satamv_chip_writeb,
55 .chip_writew = fallback_chip_writew,
56 .chip_writel = fallback_chip_writel,
57 .chip_writen = fallback_chip_writen,
58};
59
David Hendricks93784b42016-08-09 17:00:38 -070060static int satamv_shutdown(void *data)
dhendrix0ffc2eb2011-06-14 01:35:36 +000061{
62 physunmap(mv_bar, 0x20000);
63 pci_cleanup(pacc);
64 release_io_perms();
65 return 0;
66}
67
hailfinger935365d2011-02-04 21:37:59 +000068/*
69 * Random notes:
70 * FCE# Flash Chip Enable
71 * FWE# Flash Write Enable
72 * FOE# Flash Output Enable
73 * FALE[1:0] Flash Address Latch Enable
74 * FAD[7:0] Flash Multiplexed Address/Data Bus
75 * FA[2:0] Flash Address Low
76 *
77 * GPIO[15,2] GPIO Port Mode
78 * GPIO[4:3] Flash Size
79 *
80 * 0xd2c Expansion ROM BAR Control
81 * 0xc08 PCI BAR2 (Flash/NVRAM) Control
82 * 0x1046c Flash Parameters
83 */
Souvik Ghosh63b92f92016-06-29 18:45:52 -070084int satamv_init(struct flashctx *flash)
hailfinger935365d2011-02-04 21:37:59 +000085{
86 uintptr_t addr;
87 uint32_t tmp;
88
89 get_io_perms();
90
91 /* BAR0 has all internal registers memory mapped. */
92 /* No need to check for errors, pcidev_init() will not return in case
93 * of errors.
94 */
hailfinger0d703d42011-03-07 01:08:09 +000095 addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv);
hailfinger935365d2011-02-04 21:37:59 +000096
97 mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000);
98 if (mv_bar == ERROR_PTR)
99 goto error_out;
100
dhendrix0ffc2eb2011-06-14 01:35:36 +0000101 if (register_shutdown(satamv_shutdown, NULL))
102 return 1;
103
hailfinger935365d2011-02-04 21:37:59 +0000104 tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
105 msg_pspew("Flash Parameters:\n");
106 msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
107 msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
108 msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
109 msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
110 msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
111 msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
112 msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
113 msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
114 msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
115 msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
116 msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
117 msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
118 msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
119 msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
120
121 tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
122 msg_pspew("Expansion ROM BAR Control:\n");
123 msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
124
125 /* Enable BAR2 mapping to flash */
126 tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
127 msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
128 msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
129 msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
130 msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
131 tmp &= 0xffffffc0;
132 tmp |= 0x0000001f;
hailfinger1e2e3442011-05-03 21:49:41 +0000133 pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
hailfinger935365d2011-02-04 21:37:59 +0000134
135 /* Enable flash: GPIO Port Control Register 0x104f0 */
136 tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
137 msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
138 if (((tmp >> 0) & 0x3) != 0x2)
139 msg_pinfo("Warning! Either the straps are incorrect or you "
140 "have no flash or someone overwrote the strap "
141 "values!\n");
142 tmp &= 0xfffffffc;
143 tmp |= 0x2;
hailfinger1e2e3442011-05-03 21:49:41 +0000144 pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
hailfinger935365d2011-02-04 21:37:59 +0000145
146 /* Get I/O BAR location. */
147 tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) &
148 PCI_BASE_ADDRESS_IO_MASK;
149 /* Truncate to reachable range.
150 * FIXME: Check if the I/O BAR is actually reachable.
151 * This is an arch specific check.
152 */
153 mv_iobar = tmp & 0xffff;
154 msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
155
hailfinger935365d2011-02-04 21:37:59 +0000156 /* 512 kByte with two 8-bit latches, and
157 * 4 MByte with additional 3-bit latch. */
158 max_rom_decode.parallel = 4 * 1024 * 1024;
hailfinger76bb7e92011-11-09 23:40:00 +0000159 register_par_programmer(&par_programmer_satamv, BUS_PARALLEL);
hailfinger935365d2011-02-04 21:37:59 +0000160
161 return 0;
162
163error_out:
164 pci_cleanup(pacc);
165 release_io_perms();
166 return 1;
167}
168
hailfinger935365d2011-02-04 21:37:59 +0000169/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
170 * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
171 * This code only supports indirect accesses for now.
172 */
173
174/* Indirect access to via the I/O BAR1. */
175static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
176{
177 /* 0x80000000 selects BAR2 for remapping. */
178 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
179 OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
180}
181
182/* Indirect access to via the I/O BAR1. */
183static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
184{
185 /* 0x80000000 selects BAR2 for remapping. */
186 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
187 return INB(mv_iobar + 0x80 + (addr & 0x3));
188}
189
190/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700191void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
hailfinger935365d2011-02-04 21:37:59 +0000192{
193 satamv_indirect_chip_writeb(val, addr);
194}
195
196/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700197uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr)
hailfinger935365d2011-02-04 21:37:59 +0000198{
199 return satamv_indirect_chip_readb(addr);
200}
hailfingera49e9c12011-07-25 22:07:05 +0000201
202#else
203#error PCI port I/O access is not supported on this architecture yet.
204#endif