David Hendricks | d1c55d7 | 2010-08-24 15:14:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
David Hendricks | d1c55d7 | 2010-08-24 15:14:19 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 18 | #include <stdlib.h> |
| 19 | #include <string.h> |
| 20 | |
| 21 | #include "flash.h" |
| 22 | #include "flashchips.h" |
| 23 | #include "chipdrivers.h" |
Louis Yung-Chieh Lo | 52aa930 | 2010-09-06 10:45:02 +0800 | [diff] [blame] | 24 | #include "spi.h" |
David Hendricks | 23cd778 | 2010-08-25 12:42:38 -0700 | [diff] [blame] | 25 | #include "writeprotect.h" |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 26 | |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 27 | /* |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 28 | * The following procedures rely on look-up tables to match the user-specified |
| 29 | * range with the chip's supported ranges. This turned out to be the most |
| 30 | * elegant approach since diferent flash chips use different levels of |
| 31 | * granularity and methods to determine protected ranges. In other words, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 32 | * be stupid and simple since clever arithmetic will not work for many chips. |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 33 | */ |
| 34 | |
| 35 | struct wp_range { |
| 36 | unsigned int start; /* starting address */ |
| 37 | unsigned int len; /* len */ |
| 38 | }; |
| 39 | |
| 40 | enum bit_state { |
| 41 | OFF = 0, |
| 42 | ON = 1, |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 43 | X = -1 /* don't care. Must be bigger than max # of bp. */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 44 | }; |
| 45 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 46 | /* |
| 47 | * Generic write-protection schema for 25-series SPI flash chips. This assumes |
| 48 | * there is a status register that contains one or more consecutive bits which |
| 49 | * determine which address range is protected. |
| 50 | */ |
| 51 | |
| 52 | struct status_register_layout { |
| 53 | int bp0_pos; /* position of BP0 */ |
| 54 | int bp_bits; /* number of block protect bits */ |
| 55 | int srp_pos; /* position of status register protect enable bit */ |
| 56 | }; |
| 57 | |
| 58 | struct generic_range { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 59 | struct generic_modifier_bits m; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 60 | unsigned int bp; /* block protect bitfield */ |
| 61 | struct wp_range range; |
| 62 | }; |
| 63 | |
| 64 | struct generic_wp { |
| 65 | struct status_register_layout sr1; /* status register 1 */ |
| 66 | struct generic_range *ranges; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Some chips store modifier bits in one or more special control |
| 70 | * registers instead of the status register like many older SPI NOR |
| 71 | * flash chips did. get_modifier_bits() and set_modifier_bits() will do |
| 72 | * any chip-specific operations necessary to get/set these bit values. |
| 73 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 74 | int (*get_modifier_bits)(const struct flashctx *flash, |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 75 | struct generic_modifier_bits *m); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 76 | int (*set_modifier_bits)(const struct flashctx *flash, |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 77 | struct generic_modifier_bits *m); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * The following ranges and functions are useful for representing Winbond- |
| 82 | * style writeprotect schema in which there are typically 5 bits of |
| 83 | * relevant information stored in status register 1: |
| 84 | * sec: This bit indicates the units (sectors vs. blocks) |
| 85 | * tb: The top-bottom bit indicates if the affected range is at the top of |
| 86 | * the flash memory's address space or at the bottom. |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 87 | * bp: Bitmask representing the number of affected sectors/blocks. |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 88 | */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 89 | struct w25q_range { |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 90 | enum bit_state sec; /* if 1, bp bits describe sectors */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 91 | enum bit_state tb; /* top/bottom select */ |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 92 | int bp; /* block protect bitfield */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 93 | struct wp_range range; |
| 94 | }; |
| 95 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 96 | /* |
| 97 | * Mask to extract write-protect enable and range bits |
| 98 | * Status register 1: |
| 99 | * SRP0: bit 7 |
| 100 | * range(BP2-BP0): bit 4-2 |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 101 | * range(BP3-BP0): bit 5-2 (large chips) |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 102 | * Status register 2: |
| 103 | * SRP1: bit 1 |
| 104 | */ |
| 105 | #define MASK_WP_AREA (0x9C) |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 106 | #define MASK_WP_AREA_LARGE (0x9C) |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 107 | #define MASK_WP2_AREA (0x01) |
| 108 | |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 109 | struct w25q_range en25f40_ranges[] = { |
| 110 | { X, X, 0, {0, 0} }, /* none */ |
| 111 | { 0, 0, 0x1, {0x000000, 504 * 1024} }, |
| 112 | { 0, 0, 0x2, {0x000000, 496 * 1024} }, |
| 113 | { 0, 0, 0x3, {0x000000, 480 * 1024} }, |
| 114 | { 0, 0, 0x4, {0x000000, 448 * 1024} }, |
| 115 | { 0, 0, 0x5, {0x000000, 384 * 1024} }, |
| 116 | { 0, 0, 0x6, {0x000000, 256 * 1024} }, |
| 117 | { 0, 0, 0x7, {0x000000, 512 * 1024} }, |
| 118 | }; |
| 119 | |
David Hendricks | e185bf2 | 2011-05-24 15:34:18 -0700 | [diff] [blame] | 120 | struct w25q_range en25q40_ranges[] = { |
| 121 | { 0, 0, 0, {0, 0} }, /* none */ |
| 122 | { 0, 0, 0x1, {0x000000, 504 * 1024} }, |
| 123 | { 0, 0, 0x2, {0x000000, 496 * 1024} }, |
| 124 | { 0, 0, 0x3, {0x000000, 480 * 1024} }, |
| 125 | |
| 126 | { 0, 1, 0x0, {0x000000, 448 * 1024} }, |
| 127 | { 0, 1, 0x1, {0x000000, 384 * 1024} }, |
| 128 | { 0, 1, 0x2, {0x000000, 256 * 1024} }, |
| 129 | { 0, 1, 0x3, {0x000000, 512 * 1024} }, |
| 130 | }; |
| 131 | |
| 132 | struct w25q_range en25q80_ranges[] = { |
| 133 | { 0, 0, 0, {0, 0} }, /* none */ |
| 134 | { 0, 0, 0x1, {0x000000, 1016 * 1024} }, |
| 135 | { 0, 0, 0x2, {0x000000, 1008 * 1024} }, |
| 136 | { 0, 0, 0x3, {0x000000, 992 * 1024} }, |
| 137 | { 0, 0, 0x4, {0x000000, 960 * 1024} }, |
| 138 | { 0, 0, 0x5, {0x000000, 896 * 1024} }, |
| 139 | { 0, 0, 0x6, {0x000000, 768 * 1024} }, |
| 140 | { 0, 0, 0x7, {0x000000, 1024 * 1024} }, |
| 141 | }; |
| 142 | |
| 143 | struct w25q_range en25q32_ranges[] = { |
| 144 | { 0, 0, 0, {0, 0} }, /* none */ |
| 145 | { 0, 0, 0x1, {0x000000, 4032 * 1024} }, |
| 146 | { 0, 0, 0x2, {0x000000, 3968 * 1024} }, |
| 147 | { 0, 0, 0x3, {0x000000, 3840 * 1024} }, |
| 148 | { 0, 0, 0x4, {0x000000, 3584 * 1024} }, |
| 149 | { 0, 0, 0x5, {0x000000, 3072 * 1024} }, |
| 150 | { 0, 0, 0x6, {0x000000, 2048 * 1024} }, |
| 151 | { 0, 0, 0x7, {0x000000, 4096 * 1024} }, |
| 152 | |
| 153 | { 0, 1, 0, {0, 0} }, /* none */ |
| 154 | { 0, 1, 0x1, {0x010000, 4032 * 1024} }, |
| 155 | { 0, 1, 0x2, {0x020000, 3968 * 1024} }, |
| 156 | { 0, 1, 0x3, {0x040000, 3840 * 1024} }, |
| 157 | { 0, 1, 0x4, {0x080000, 3584 * 1024} }, |
| 158 | { 0, 1, 0x5, {0x100000, 3072 * 1024} }, |
| 159 | { 0, 1, 0x6, {0x200000, 2048 * 1024} }, |
| 160 | { 0, 1, 0x7, {0x000000, 4096 * 1024} }, |
| 161 | }; |
| 162 | |
| 163 | struct w25q_range en25q64_ranges[] = { |
| 164 | { 0, 0, 0, {0, 0} }, /* none */ |
| 165 | { 0, 0, 0x1, {0x000000, 8128 * 1024} }, |
| 166 | { 0, 0, 0x2, {0x000000, 8064 * 1024} }, |
| 167 | { 0, 0, 0x3, {0x000000, 7936 * 1024} }, |
| 168 | { 0, 0, 0x4, {0x000000, 7680 * 1024} }, |
| 169 | { 0, 0, 0x5, {0x000000, 7168 * 1024} }, |
| 170 | { 0, 0, 0x6, {0x000000, 6144 * 1024} }, |
| 171 | { 0, 0, 0x7, {0x000000, 8192 * 1024} }, |
| 172 | |
| 173 | { 0, 1, 0, {0, 0} }, /* none */ |
| 174 | { 0, 1, 0x1, {0x010000, 8128 * 1024} }, |
| 175 | { 0, 1, 0x2, {0x020000, 8064 * 1024} }, |
| 176 | { 0, 1, 0x3, {0x040000, 7936 * 1024} }, |
| 177 | { 0, 1, 0x4, {0x080000, 7680 * 1024} }, |
| 178 | { 0, 1, 0x5, {0x100000, 7168 * 1024} }, |
| 179 | { 0, 1, 0x6, {0x200000, 6144 * 1024} }, |
| 180 | { 0, 1, 0x7, {0x000000, 8192 * 1024} }, |
| 181 | }; |
| 182 | |
| 183 | struct w25q_range en25q128_ranges[] = { |
| 184 | { 0, 0, 0, {0, 0} }, /* none */ |
| 185 | { 0, 0, 0x1, {0x000000, 16320 * 1024} }, |
| 186 | { 0, 0, 0x2, {0x000000, 16256 * 1024} }, |
| 187 | { 0, 0, 0x3, {0x000000, 16128 * 1024} }, |
| 188 | { 0, 0, 0x4, {0x000000, 15872 * 1024} }, |
| 189 | { 0, 0, 0x5, {0x000000, 15360 * 1024} }, |
| 190 | { 0, 0, 0x6, {0x000000, 14336 * 1024} }, |
| 191 | { 0, 0, 0x7, {0x000000, 16384 * 1024} }, |
| 192 | |
| 193 | { 0, 1, 0, {0, 0} }, /* none */ |
| 194 | { 0, 1, 0x1, {0x010000, 16320 * 1024} }, |
| 195 | { 0, 1, 0x2, {0x020000, 16256 * 1024} }, |
| 196 | { 0, 1, 0x3, {0x040000, 16128 * 1024} }, |
| 197 | { 0, 1, 0x4, {0x080000, 15872 * 1024} }, |
| 198 | { 0, 1, 0x5, {0x100000, 15360 * 1024} }, |
| 199 | { 0, 1, 0x6, {0x200000, 14336 * 1024} }, |
| 200 | { 0, 1, 0x7, {0x000000, 16384 * 1024} }, |
| 201 | }; |
| 202 | |
Marc Jones | b2f9002 | 2014-04-29 17:37:23 -0600 | [diff] [blame] | 203 | struct w25q_range en25s64_ranges[] = { |
| 204 | { 0, 0, 0, {0, 0} }, /* none */ |
| 205 | { 0, 0, 0x1, {0x000000, 8064 * 1024} }, |
| 206 | { 0, 0, 0x2, {0x000000, 7936 * 1024} }, |
| 207 | { 0, 0, 0x3, {0x000000, 7680 * 1024} }, |
| 208 | { 0, 0, 0x4, {0x000000, 7168 * 1024} }, |
| 209 | { 0, 0, 0x5, {0x000000, 6144 * 1024} }, |
| 210 | { 0, 0, 0x6, {0x000000, 4096 * 1024} }, |
| 211 | { 0, 0, 0x7, {0x000000, 8192 * 1024} }, |
| 212 | |
| 213 | { 0, 1, 0, {0, 0} }, /* none */ |
| 214 | { 0, 1, 0x1, {0x7e0000, 128 * 1024} }, |
| 215 | { 0, 1, 0x2, {0x7c0000, 256 * 1024} }, |
| 216 | { 0, 1, 0x3, {0x780000, 512 * 1024} }, |
| 217 | { 0, 1, 0x4, {0x700000, 1024 * 1024} }, |
| 218 | { 0, 1, 0x5, {0x600000, 2048 * 1024} }, |
| 219 | { 0, 1, 0x6, {0x400000, 4096 * 1024} }, |
| 220 | { 0, 1, 0x7, {0x000000, 8192 * 1024} }, |
| 221 | }; |
| 222 | |
David Hendricks | f8f00c7 | 2011-02-01 12:39:46 -0800 | [diff] [blame] | 223 | /* mx25l1005 ranges also work for the mx25l1005c */ |
| 224 | static struct w25q_range mx25l1005_ranges[] = { |
| 225 | { X, X, 0, {0, 0} }, /* none */ |
| 226 | { X, X, 0x1, {0x010000, 64 * 1024} }, |
| 227 | { X, X, 0x2, {0x000000, 128 * 1024} }, |
| 228 | { X, X, 0x3, {0x000000, 128 * 1024} }, |
| 229 | }; |
| 230 | |
| 231 | static struct w25q_range mx25l2005_ranges[] = { |
| 232 | { X, X, 0, {0, 0} }, /* none */ |
| 233 | { X, X, 0x1, {0x030000, 64 * 1024} }, |
| 234 | { X, X, 0x2, {0x020000, 128 * 1024} }, |
| 235 | { X, X, 0x3, {0x000000, 256 * 1024} }, |
| 236 | }; |
| 237 | |
| 238 | static struct w25q_range mx25l4005_ranges[] = { |
| 239 | { X, X, 0, {0, 0} }, /* none */ |
| 240 | { X, X, 0x1, {0x070000, 64 * 1 * 1024} }, /* block 7 */ |
| 241 | { X, X, 0x2, {0x060000, 64 * 2 * 1024} }, /* blocks 6-7 */ |
| 242 | { X, X, 0x3, {0x040000, 64 * 4 * 1024} }, /* blocks 4-7 */ |
| 243 | { X, X, 0x4, {0x000000, 512 * 1024} }, |
| 244 | { X, X, 0x5, {0x000000, 512 * 1024} }, |
| 245 | { X, X, 0x6, {0x000000, 512 * 1024} }, |
| 246 | { X, X, 0x7, {0x000000, 512 * 1024} }, |
| 247 | }; |
| 248 | |
| 249 | static struct w25q_range mx25l8005_ranges[] = { |
| 250 | { X, X, 0, {0, 0} }, /* none */ |
| 251 | { X, X, 0x1, {0x0f0000, 64 * 1 * 1024} }, /* block 15 */ |
| 252 | { X, X, 0x2, {0x0e0000, 64 * 2 * 1024} }, /* blocks 14-15 */ |
| 253 | { X, X, 0x3, {0x0c0000, 64 * 4 * 1024} }, /* blocks 12-15 */ |
| 254 | { X, X, 0x4, {0x080000, 64 * 8 * 1024} }, /* blocks 8-15 */ |
| 255 | { X, X, 0x5, {0x000000, 1024 * 1024} }, |
| 256 | { X, X, 0x6, {0x000000, 1024 * 1024} }, |
| 257 | { X, X, 0x7, {0x000000, 1024 * 1024} }, |
| 258 | }; |
| 259 | |
| 260 | #if 0 |
| 261 | /* FIXME: mx25l1605 has the same IDs as the mx25l1605d */ |
| 262 | static struct w25q_range mx25l1605_ranges[] = { |
| 263 | { X, X, 0, {0, 0} }, /* none */ |
| 264 | { X, X, 0x1, {0x1f0000, 64 * 1024} }, /* block 31 */ |
| 265 | { X, X, 0x2, {0x1e0000, 128 * 1024} }, /* blocks 30-31 */ |
| 266 | { X, X, 0x3, {0x1c0000, 256 * 1024} }, /* blocks 28-31 */ |
| 267 | { X, X, 0x4, {0x180000, 512 * 1024} }, /* blocks 24-31 */ |
| 268 | { X, X, 0x4, {0x100000, 1024 * 1024} }, /* blocks 16-31 */ |
| 269 | { X, X, 0x6, {0x000000, 2048 * 1024} }, |
| 270 | { X, X, 0x7, {0x000000, 2048 * 1024} }, |
| 271 | }; |
| 272 | #endif |
| 273 | |
| 274 | #if 0 |
| 275 | /* FIXME: mx25l6405 has the same IDs as the mx25l6405d */ |
| 276 | static struct w25q_range mx25l6405_ranges[] = { |
| 277 | { X, 0, 0, {0, 0} }, /* none */ |
| 278 | { X, 0, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */ |
| 279 | { X, 0, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */ |
| 280 | { X, 0, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */ |
| 281 | { X, 0, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */ |
| 282 | { X, 0, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */ |
| 283 | { X, 0, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */ |
| 284 | { X, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 285 | |
| 286 | { X, 1, 0x0, {0x000000, 8192 * 1024} }, |
| 287 | { X, 1, 0x1, {0x000000, 8192 * 1024} }, |
| 288 | { X, 1, 0x2, {0x000000, 8192 * 1024} }, |
| 289 | { X, 1, 0x3, {0x000000, 8192 * 1024} }, |
| 290 | { X, 1, 0x4, {0x000000, 8192 * 1024} }, |
| 291 | { X, 1, 0x5, {0x000000, 8192 * 1024} }, |
| 292 | { X, 1, 0x6, {0x000000, 8192 * 1024} }, |
| 293 | { X, 1, 0x7, {0x000000, 8192 * 1024} }, |
| 294 | }; |
| 295 | #endif |
| 296 | |
| 297 | static struct w25q_range mx25l1605d_ranges[] = { |
| 298 | { X, 0, 0, {0, 0} }, /* none */ |
| 299 | { X, 0, 0x1, {0x1f0000, 64 * 1 * 1024} }, /* block 31 */ |
| 300 | { X, 0, 0x2, {0x1e0000, 64 * 2 * 1024} }, /* blocks 30-31 */ |
| 301 | { X, 0, 0x3, {0x1c0000, 64 * 4 * 1024} }, /* blocks 28-31 */ |
| 302 | { X, 0, 0x4, {0x180000, 64 * 8 * 1024} }, /* blocks 24-31 */ |
| 303 | { X, 0, 0x5, {0x100000, 64 * 16 * 1024} }, /* blocks 16-31 */ |
| 304 | { X, 0, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 305 | { X, 0, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 306 | |
| 307 | { X, 1, 0x0, {0x000000, 2048 * 1024} }, |
| 308 | { X, 1, 0x1, {0x000000, 2048 * 1024} }, |
| 309 | { X, 1, 0x2, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */ |
| 310 | { X, 1, 0x3, {0x000000, 64 * 24 * 1024} }, /* blocks 0-23 */ |
| 311 | { X, 1, 0x4, {0x000000, 64 * 28 * 1024} }, /* blocks 0-27 */ |
| 312 | { X, 1, 0x5, {0x000000, 64 * 30 * 1024} }, /* blocks 0-29 */ |
| 313 | { X, 1, 0x6, {0x000000, 64 * 31 * 1024} }, /* blocks 0-30 */ |
| 314 | { X, 1, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 315 | }; |
| 316 | |
| 317 | /* FIXME: Is there an mx25l3205 (without a trailing letter)? */ |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 318 | static struct w25q_range mx25l3205d_ranges[] = { |
| 319 | { X, 0, 0, {0, 0} }, /* none */ |
| 320 | { X, 0, 0x1, {0x3f0000, 64 * 1024} }, |
| 321 | { X, 0, 0x2, {0x3e0000, 128 * 1024} }, |
| 322 | { X, 0, 0x3, {0x3c0000, 256 * 1024} }, |
| 323 | { X, 0, 0x4, {0x380000, 512 * 1024} }, |
| 324 | { X, 0, 0x5, {0x300000, 1024 * 1024} }, |
| 325 | { X, 0, 0x6, {0x200000, 2048 * 1024} }, |
| 326 | { X, 0, 0x7, {0x000000, 4096 * 1024} }, |
| 327 | |
| 328 | { X, 1, 0x0, {0x000000, 4096 * 1024} }, |
| 329 | { X, 1, 0x1, {0x000000, 2048 * 1024} }, |
| 330 | { X, 1, 0x2, {0x000000, 3072 * 1024} }, |
| 331 | { X, 1, 0x3, {0x000000, 3584 * 1024} }, |
| 332 | { X, 1, 0x4, {0x000000, 3840 * 1024} }, |
| 333 | { X, 1, 0x5, {0x000000, 3968 * 1024} }, |
| 334 | { X, 1, 0x6, {0x000000, 4032 * 1024} }, |
| 335 | { X, 1, 0x7, {0x000000, 4096 * 1024} }, |
| 336 | }; |
| 337 | |
Vincent Palatin | 87e092a | 2013-02-28 15:46:14 -0800 | [diff] [blame] | 338 | static struct w25q_range mx25u3235e_ranges[] = { |
| 339 | { X, 0, 0, {0, 0} }, /* none */ |
| 340 | { 0, 0, 0x1, {0x3f0000, 64 * 1024} }, |
| 341 | { 0, 0, 0x2, {0x3e0000, 128 * 1024} }, |
| 342 | { 0, 0, 0x3, {0x3c0000, 256 * 1024} }, |
| 343 | { 0, 0, 0x4, {0x380000, 512 * 1024} }, |
| 344 | { 0, 0, 0x5, {0x300000, 1024 * 1024} }, |
| 345 | { 0, 0, 0x6, {0x200000, 2048 * 1024} }, |
| 346 | { 0, 0, 0x7, {0x000000, 4096 * 1024} }, |
| 347 | |
| 348 | { 0, 1, 0x0, {0x000000, 4096 * 1024} }, |
| 349 | { 0, 1, 0x1, {0x000000, 2048 * 1024} }, |
| 350 | { 0, 1, 0x2, {0x000000, 3072 * 1024} }, |
| 351 | { 0, 1, 0x3, {0x000000, 3584 * 1024} }, |
| 352 | { 0, 1, 0x4, {0x000000, 3840 * 1024} }, |
| 353 | { 0, 1, 0x5, {0x000000, 3968 * 1024} }, |
| 354 | { 0, 1, 0x6, {0x000000, 4032 * 1024} }, |
| 355 | { 0, 1, 0x7, {0x000000, 4096 * 1024} }, |
| 356 | }; |
| 357 | |
Jongpil | 66a9649 | 2014-08-14 17:59:06 +0900 | [diff] [blame] | 358 | static struct w25q_range mx25u6435e_ranges[] = { |
| 359 | { X, 0, 0, {0, 0} }, /* none */ |
| 360 | { 0, 0, 0x1, {0x7f0000, 1 * 64 * 1024} }, /* block 127 */ |
| 361 | { 0, 0, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */ |
| 362 | { 0, 0, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */ |
| 363 | { 0, 0, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */ |
| 364 | { 0, 0, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */ |
| 365 | { 0, 0, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */ |
| 366 | { 0, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 367 | |
| 368 | { 0, 1, 0x0, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 369 | { 0, 1, 0x1, {0x000000, 96 * 64 * 1024} }, /* blocks 0-95 */ |
| 370 | { 0, 1, 0x2, {0x000000, 112 * 64 * 1024} }, /* blocks 0-111 */ |
| 371 | { 0, 1, 0x3, {0x000000, 120 * 64 * 1024} }, /* blocks 0-119 */ |
| 372 | { 0, 1, 0x4, {0x000000, 124 * 64 * 1024} }, /* blocks 0-123 */ |
| 373 | { 0, 1, 0x5, {0x000000, 126 * 64 * 1024} }, /* blocks 0-125 */ |
| 374 | { 0, 1, 0x6, {0x000000, 127 * 64 * 1024} }, /* blocks 0-126 */ |
| 375 | { 0, 1, 0x7, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */ |
| 376 | }; |
| 377 | |
Alex Lu | 831c609 | 2017-11-02 23:19:34 -0700 | [diff] [blame] | 378 | static struct w25q_range mx25u12835f_ranges[] = { |
Paul Fagerburg | 9057158 | 2019-03-15 11:32:57 -0600 | [diff] [blame] | 379 | { X, X, 0, {0, 0} }, /* none */ |
Alex Lu | 831c609 | 2017-11-02 23:19:34 -0700 | [diff] [blame] | 380 | { 0, 0, 0x1, {0xff0000, 1 * 64 * 1024} }, /* block 255 */ |
| 381 | { 0, 0, 0x2, {0xfe0000, 2 * 64 * 1024} }, /* blocks 254-255 */ |
| 382 | { 0, 0, 0x3, {0xfc0000, 4 * 64 * 1024} }, /* blocks 252-255 */ |
| 383 | { 0, 0, 0x4, {0xf80000, 8 * 64 * 1024} }, /* blocks 248-255 */ |
| 384 | { 0, 0, 0x5, {0xf00000, 16 * 64 * 1024} }, /* blocks 240-255 */ |
| 385 | { 0, 0, 0x6, {0xe00000, 32 * 64 * 1024} }, /* blocks 224-255 */ |
| 386 | { 0, 0, 0x7, {0xc00000, 64 * 64 * 1024} }, /* blocks 192-255 */ |
Paul Fagerburg | 9057158 | 2019-03-15 11:32:57 -0600 | [diff] [blame] | 387 | { 0, 0, 0x8, {0x800000, 128 * 64 * 1024} }, /* blocks 128-255 */ |
| 388 | { 0, 0, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 389 | { 0, 0, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 390 | { 0, 0, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 391 | { 0, 0, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 392 | { 0, 0, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 393 | { 0, 0, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 394 | { 0, 0, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
Alex Lu | 831c609 | 2017-11-02 23:19:34 -0700 | [diff] [blame] | 395 | |
Paul Fagerburg | 9057158 | 2019-03-15 11:32:57 -0600 | [diff] [blame] | 396 | { 0, 1, 0x1, {0x000000, 1 * 64 * 1024} }, /* block 0 */ |
| 397 | { 0, 1, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */ |
| 398 | { 0, 1, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */ |
| 399 | { 0, 1, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */ |
| 400 | { 0, 1, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */ |
| 401 | { 0, 1, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */ |
| 402 | { 0, 1, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 403 | { 0, 1, 0x8, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */ |
| 404 | { 0, 1, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 405 | { 0, 1, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 406 | { 0, 1, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 407 | { 0, 1, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 408 | { 0, 1, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 409 | { 0, 1, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
| 410 | { 0, 1, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */ |
Alex Lu | 831c609 | 2017-11-02 23:19:34 -0700 | [diff] [blame] | 411 | }; |
| 412 | |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 413 | static struct w25q_range n25q064_ranges[] = { |
David Hendricks | fe9123b | 2015-04-21 13:18:31 -0700 | [diff] [blame] | 414 | /* |
| 415 | * Note: For N25Q064, sec (usually in bit position 6) is called BP3 |
| 416 | * (block protect bit 3). It is only useful when all blocks are to |
| 417 | * be write-protected. |
| 418 | */ |
David Hendricks | 42a549a | 2015-04-22 11:25:07 -0700 | [diff] [blame] | 419 | { 0, 0, 0, {0, 0} }, /* none */ |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 420 | |
| 421 | { 0, 0, 0x1, {0x7f0000, 64 * 1024} }, /* block 127 */ |
| 422 | { 0, 0, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */ |
| 423 | { 0, 0, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */ |
| 424 | { 0, 0, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */ |
| 425 | { 0, 0, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */ |
| 426 | { 0, 0, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */ |
| 427 | { 0, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 428 | |
David Hendricks | fe9123b | 2015-04-21 13:18:31 -0700 | [diff] [blame] | 429 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, /* block 0 */ |
| 430 | { 0, 1, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */ |
| 431 | { 0, 1, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */ |
| 432 | { 0, 1, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */ |
| 433 | { 0, 1, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */ |
| 434 | { 0, 1, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */ |
| 435 | { 0, 1, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 436 | |
| 437 | { X, 1, 0x0, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 438 | { X, 1, 0x1, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 439 | { X, 1, 0x2, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 440 | { X, 1, 0x3, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 441 | { X, 1, 0x4, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 442 | { X, 1, 0x5, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 443 | { X, 1, 0x6, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 444 | { X, 1, 0x7, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 445 | }; |
| 446 | |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 447 | static struct w25q_range w25q16_ranges[] = { |
| 448 | { X, X, 0, {0, 0} }, /* none */ |
| 449 | { 0, 0, 0x1, {0x1f0000, 64 * 1024} }, |
| 450 | { 0, 0, 0x2, {0x1e0000, 128 * 1024} }, |
| 451 | { 0, 0, 0x3, {0x1c0000, 256 * 1024} }, |
| 452 | { 0, 0, 0x4, {0x180000, 512 * 1024} }, |
| 453 | { 0, 0, 0x5, {0x100000, 1024 * 1024} }, |
| 454 | |
| 455 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 456 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 457 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 458 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
| 459 | { 0, 1, 0x5, {0x000000, 1024 * 1024} }, |
| 460 | { X, X, 0x6, {0x000000, 2048 * 1024} }, |
| 461 | { X, X, 0x7, {0x000000, 2048 * 1024} }, |
| 462 | |
| 463 | { 1, 0, 0x1, {0x1ff000, 4 * 1024} }, |
| 464 | { 1, 0, 0x2, {0x1fe000, 8 * 1024} }, |
| 465 | { 1, 0, 0x3, {0x1fc000, 16 * 1024} }, |
| 466 | { 1, 0, 0x4, {0x1f8000, 32 * 1024} }, |
Paul Fagerburg | 9057158 | 2019-03-15 11:32:57 -0600 | [diff] [blame] | 467 | { 1, 0, 0x5, {0x1f8000, 32 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 468 | |
| 469 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 470 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 471 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
Paul Fagerburg | 9057158 | 2019-03-15 11:32:57 -0600 | [diff] [blame] | 472 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 473 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 474 | }; |
| 475 | |
| 476 | static struct w25q_range w25q32_ranges[] = { |
| 477 | { X, X, 0, {0, 0} }, /* none */ |
| 478 | { 0, 0, 0x1, {0x3f0000, 64 * 1024} }, |
| 479 | { 0, 0, 0x2, {0x3e0000, 128 * 1024} }, |
| 480 | { 0, 0, 0x3, {0x3c0000, 256 * 1024} }, |
| 481 | { 0, 0, 0x4, {0x380000, 512 * 1024} }, |
| 482 | { 0, 0, 0x5, {0x300000, 1024 * 1024} }, |
David Hendricks | 05653ff | 2010-06-15 16:05:12 -0700 | [diff] [blame] | 483 | { 0, 0, 0x6, {0x200000, 2048 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 484 | |
| 485 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 486 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 487 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 488 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
| 489 | { 0, 1, 0x5, {0x000000, 1024 * 1024} }, |
| 490 | { 0, 1, 0x6, {0x000000, 2048 * 1024} }, |
| 491 | { X, X, 0x7, {0x000000, 4096 * 1024} }, |
| 492 | |
| 493 | { 1, 0, 0x1, {0x3ff000, 4 * 1024} }, |
| 494 | { 1, 0, 0x2, {0x3fe000, 8 * 1024} }, |
| 495 | { 1, 0, 0x3, {0x3fc000, 16 * 1024} }, |
| 496 | { 1, 0, 0x4, {0x3f8000, 32 * 1024} }, |
Paul Fagerburg | 9057158 | 2019-03-15 11:32:57 -0600 | [diff] [blame] | 497 | { 1, 0, 0x5, {0x3f8000, 32 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 498 | |
| 499 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 500 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 501 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 502 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 503 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 504 | }; |
| 505 | |
| 506 | static struct w25q_range w25q80_ranges[] = { |
| 507 | { X, X, 0, {0, 0} }, /* none */ |
| 508 | { 0, 0, 0x1, {0x0f0000, 64 * 1024} }, |
| 509 | { 0, 0, 0x2, {0x0e0000, 128 * 1024} }, |
| 510 | { 0, 0, 0x3, {0x0c0000, 256 * 1024} }, |
| 511 | { 0, 0, 0x4, {0x080000, 512 * 1024} }, |
| 512 | |
| 513 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 514 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 515 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 516 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
David Hendricks | 05653ff | 2010-06-15 16:05:12 -0700 | [diff] [blame] | 517 | { X, X, 0x6, {0x000000, 1024 * 1024} }, |
| 518 | { X, X, 0x7, {0x000000, 1024 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 519 | |
| 520 | { 1, 0, 0x1, {0x1ff000, 4 * 1024} }, |
| 521 | { 1, 0, 0x2, {0x1fe000, 8 * 1024} }, |
| 522 | { 1, 0, 0x3, {0x1fc000, 16 * 1024} }, |
| 523 | { 1, 0, 0x4, {0x1f8000, 32 * 1024} }, |
| 524 | { 1, 0, 0x5, {0x1f8000, 32 * 1024} }, |
| 525 | |
| 526 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 527 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 528 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 529 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 530 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 531 | }; |
| 532 | |
David Hendricks | 2c4a76c | 2010-06-28 14:00:43 -0700 | [diff] [blame] | 533 | static struct w25q_range w25q64_ranges[] = { |
| 534 | { X, X, 0, {0, 0} }, /* none */ |
| 535 | |
| 536 | { 0, 0, 0x1, {0x7e0000, 128 * 1024} }, |
| 537 | { 0, 0, 0x2, {0x7c0000, 256 * 1024} }, |
| 538 | { 0, 0, 0x3, {0x780000, 512 * 1024} }, |
| 539 | { 0, 0, 0x4, {0x700000, 1024 * 1024} }, |
| 540 | { 0, 0, 0x5, {0x600000, 2048 * 1024} }, |
| 541 | { 0, 0, 0x6, {0x400000, 4096 * 1024} }, |
| 542 | |
| 543 | { 0, 1, 0x1, {0x000000, 128 * 1024} }, |
| 544 | { 0, 1, 0x2, {0x000000, 256 * 1024} }, |
| 545 | { 0, 1, 0x3, {0x000000, 512 * 1024} }, |
| 546 | { 0, 1, 0x4, {0x000000, 1024 * 1024} }, |
| 547 | { 0, 1, 0x5, {0x000000, 2048 * 1024} }, |
| 548 | { 0, 1, 0x6, {0x000000, 4096 * 1024} }, |
| 549 | { X, X, 0x7, {0x000000, 8192 * 1024} }, |
| 550 | |
| 551 | { 1, 0, 0x1, {0x7ff000, 4 * 1024} }, |
| 552 | { 1, 0, 0x2, {0x7fe000, 8 * 1024} }, |
| 553 | { 1, 0, 0x3, {0x7fc000, 16 * 1024} }, |
| 554 | { 1, 0, 0x4, {0x7f8000, 32 * 1024} }, |
| 555 | { 1, 0, 0x5, {0x7f8000, 32 * 1024} }, |
| 556 | |
| 557 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 558 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 559 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 560 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 561 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 562 | }; |
| 563 | |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 564 | static struct w25q_range w25rq128_cmp0_ranges[] = { |
| 565 | { X, X, 0, {0, 0} }, /* NONE */ |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 566 | |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 567 | { 0, 0, 0x1, {0xfc0000, 256 * 1024} }, /* Upper 1/64 */ |
| 568 | { 0, 0, 0x2, {0xf80000, 512 * 1024} }, /* Upper 1/32 */ |
| 569 | { 0, 0, 0x3, {0xf00000, 1024 * 1024} }, /* Upper 1/16 */ |
| 570 | { 0, 0, 0x4, {0xe00000, 2048 * 1024} }, /* Upper 1/8 */ |
| 571 | { 0, 0, 0x5, {0xc00000, 4096 * 1024} }, /* Upper 1/4 */ |
| 572 | { 0, 0, 0x6, {0x800000, 8192 * 1024} }, /* Upper 1/2 */ |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 573 | |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 574 | { 0, 1, 0x1, {0x000000, 256 * 1024} }, /* Lower 1/64 */ |
| 575 | { 0, 1, 0x2, {0x000000, 512 * 1024} }, /* Lower 1/32 */ |
| 576 | { 0, 1, 0x3, {0x000000, 1024 * 1024} }, /* Lower 1/16 */ |
| 577 | { 0, 1, 0x4, {0x000000, 2048 * 1024} }, /* Lower 1/8 */ |
| 578 | { 0, 1, 0x5, {0x000000, 4096 * 1024} }, /* Lower 1/4 */ |
| 579 | { 0, 1, 0x6, {0x000000, 8192 * 1024} }, /* Lower 1/2 */ |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 580 | |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 581 | { X, X, 0x7, {0x000000, 16384 * 1024} }, /* ALL */ |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 582 | |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 583 | { 1, 0, 0x1, {0xfff000, 4 * 1024} }, /* Upper 1/4096 */ |
| 584 | { 1, 0, 0x2, {0xffe000, 8 * 1024} }, /* Upper 1/2048 */ |
| 585 | { 1, 0, 0x3, {0xffc000, 16 * 1024} }, /* Upper 1/1024 */ |
| 586 | { 1, 0, 0x4, {0xff8000, 32 * 1024} }, /* Upper 1/512 */ |
| 587 | { 1, 0, 0x5, {0xff8000, 32 * 1024} }, /* Upper 1/512 */ |
| 588 | |
| 589 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, /* Lower 1/4096 */ |
| 590 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, /* Lower 1/2048 */ |
| 591 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, /* Lower 1/1024 */ |
| 592 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, /* Lower 1/512 */ |
| 593 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, /* Lower 1/512 */ |
| 594 | }; |
| 595 | |
| 596 | static struct w25q_range w25rq128_cmp1_ranges[] = { |
| 597 | { X, X, 0x0, {0x000000, 16 * 1024 * 1024} }, /* ALL */ |
| 598 | |
| 599 | { 0, 0, 0x1, {0x000000, 16128 * 1024} }, /* Lower 63/64 */ |
| 600 | { 0, 0, 0x2, {0x000000, 15872 * 1024} }, /* Lower 31/32 */ |
| 601 | { 0, 0, 0x3, {0x000000, 15 * 1024 * 1024} }, /* Lower 15/16 */ |
| 602 | { 0, 0, 0x4, {0x000000, 14 * 1024 * 1024} }, /* Lower 7/8 */ |
| 603 | { 0, 0, 0x5, {0x000000, 12 * 1024 * 1024} }, /* Lower 3/4 */ |
| 604 | { 0, 0, 0x6, {0x000000, 8 * 1024 * 1024} }, /* Lower 1/2 */ |
| 605 | |
| 606 | { 0, 1, 0x1, {0x040000, 16128 * 1024} }, /* Upper 63/64 */ |
| 607 | { 0, 1, 0x2, {0x080000, 15872 * 1024} }, /* Upper 31/32 */ |
| 608 | { 0, 1, 0x3, {0x100000, 15 * 1024 * 1024} }, /* Upper 15/16 */ |
| 609 | { 0, 1, 0x4, {0x200000, 14 * 1024 * 1024} }, /* Upper 7/8 */ |
| 610 | { 0, 1, 0x5, {0x400000, 12 * 1024 * 1024} }, /* Upper 3/4 */ |
| 611 | { 0, 1, 0x6, {0x800000, 8 * 1024 * 1024} }, /* Upper 1/2 */ |
| 612 | |
| 613 | { X, X, 0x7, {0x000000, 0} }, /* NONE */ |
| 614 | |
| 615 | { 1, 0, 0x1, {0x000000, 16380 * 1024} }, /* Lower 4095/4096 */ |
| 616 | { 1, 0, 0x2, {0x000000, 16376 * 1024} }, /* Lower 2048/2048 */ |
| 617 | { 1, 0, 0x3, {0x000000, 16368 * 1024} }, /* Lower 1023/1024 */ |
| 618 | { 1, 0, 0x4, {0x000000, 16352 * 1024} }, /* Lower 511/512 */ |
| 619 | { 1, 0, 0x5, {0x000000, 16352 * 1024} }, /* Lower 511/512 */ |
| 620 | |
| 621 | { 1, 1, 0x1, {0x001000, 16380 * 1024} }, /* Upper 4095/4096 */ |
| 622 | { 1, 1, 0x2, {0x002000, 16376 * 1024} }, /* Upper 2047/2048 */ |
| 623 | { 1, 1, 0x3, {0x004000, 16368 * 1024} }, /* Upper 1023/1024 */ |
| 624 | { 1, 1, 0x4, {0x008000, 16352 * 1024} }, /* Upper 511/512 */ |
| 625 | { 1, 1, 0x5, {0x008000, 16352 * 1024} }, /* Upper 511/512 */ |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 626 | }; |
| 627 | |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 628 | static struct w25q_range w25rq256_cmp0_ranges[] = { |
| 629 | { X, X, 0x0, {0x0000000, 0x0000000} }, /* NONE */ |
| 630 | |
| 631 | { X, 0, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* Upper 1/512 */ |
| 632 | { X, 0, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* Upper 1/256 */ |
| 633 | { X, 0, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* Upper 1/128 */ |
| 634 | { X, 0, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* Upper 1/64 */ |
| 635 | { X, 0, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* Upper 1/32 */ |
| 636 | { X, 0, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* Upper 1/16 */ |
| 637 | { X, 0, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* Upper 1/8 */ |
| 638 | { X, 0, 0x8, {0x1800000, 64 * 128 * 1024} }, /* Upper 1/4 */ |
| 639 | { X, 0, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */ |
| 640 | |
| 641 | { X, 1, 0x1, {0x0000000, 64 * 1 * 1024} }, /* Lower 1/512 */ |
| 642 | { X, 1, 0x2, {0x0000000, 64 * 2 * 1024} }, /* Lower 1/256 */ |
| 643 | { X, 1, 0x3, {0x0000000, 64 * 4 * 1024} }, /* Lower 1/128 */ |
| 644 | { X, 1, 0x4, {0x0000000, 64 * 8 * 1024} }, /* Lower 1/64 */ |
| 645 | { X, 1, 0x5, {0x0000000, 64 * 16 * 1024} }, /* Lower 1/32 */ |
| 646 | { X, 1, 0x6, {0x0000000, 64 * 32 * 1024} }, /* Lower 1/16 */ |
| 647 | { X, 1, 0x7, {0x0000000, 64 * 64 * 1024} }, /* Lower 1/8 */ |
| 648 | { X, 1, 0x8, {0x0000000, 64 * 128 * 1024} }, /* Lower 1/4 */ |
| 649 | { X, 1, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */ |
| 650 | |
| 651 | { X, X, 0xa, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 652 | { X, X, 0xb, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 653 | { X, X, 0xc, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 654 | { X, X, 0xd, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 655 | { X, X, 0xe, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 656 | { X, X, 0xf, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 657 | }; |
| 658 | |
| 659 | static struct w25q_range w25rq256_cmp1_ranges[] = { |
| 660 | { X, X, 0x0, {0x0000000, 64 * 512 * 1024} }, /* ALL */ |
| 661 | |
| 662 | { X, 0, 0x1, {0x0000000, 64 * 511 * 1024} }, /* Lower 511/512 */ |
| 663 | { X, 0, 0x2, {0x0000000, 64 * 510 * 1024} }, /* Lower 255/256 */ |
| 664 | { X, 0, 0x3, {0x0000000, 64 * 508 * 1024} }, /* Lower 127/128 */ |
| 665 | { X, 0, 0x4, {0x0000000, 64 * 504 * 1024} }, /* Lower 63/64 */ |
| 666 | { X, 0, 0x5, {0x0000000, 64 * 496 * 1024} }, /* Lower 31/32 */ |
| 667 | { X, 0, 0x6, {0x0000000, 64 * 480 * 1024} }, /* Lower 15/16 */ |
| 668 | { X, 0, 0x7, {0x0000000, 64 * 448 * 1024} }, /* Lower 7/8 */ |
| 669 | { X, 0, 0x8, {0x0000000, 64 * 384 * 1024} }, /* Lower 3/4 */ |
| 670 | { X, 0, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */ |
| 671 | |
| 672 | { X, 1, 0x1, {0x0010000, 64 * 511 * 1024} }, /* Upper 511/512 */ |
| 673 | { X, 1, 0x2, {0x0020000, 64 * 510 * 1024} }, /* Upper 255/256 */ |
| 674 | { X, 1, 0x3, {0x0040000, 64 * 508 * 1024} }, /* Upper 127/128 */ |
| 675 | { X, 1, 0x4, {0x0080000, 64 * 504 * 1024} }, /* Upper 63/64 */ |
| 676 | { X, 1, 0x5, {0x0100000, 64 * 496 * 1024} }, /* Upper 31/32 */ |
| 677 | { X, 1, 0x6, {0x0200000, 64 * 480 * 1024} }, /* Upper 15/16 */ |
| 678 | { X, 1, 0x7, {0x0400000, 64 * 448 * 1024} }, /* Upper 7/8 */ |
| 679 | { X, 1, 0x8, {0x0800000, 64 * 384 * 1024} }, /* Upper 3/4 */ |
| 680 | { X, 1, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */ |
| 681 | |
| 682 | { X, X, 0xa, {0x0000000, 0x0000000} }, /* NONE */ |
| 683 | { X, X, 0xb, {0x0000000, 0x0000000} }, /* NONE */ |
| 684 | { X, X, 0xc, {0x0000000, 0x0000000} }, /* NONE */ |
| 685 | { X, X, 0xd, {0x0000000, 0x0000000} }, /* NONE */ |
| 686 | { X, X, 0xe, {0x0000000, 0x0000000} }, /* NONE */ |
| 687 | { X, X, 0xf, {0x0000000, 0x0000000} }, /* NONE */ |
| 688 | }; |
| 689 | |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 690 | struct w25q_range w25x10_ranges[] = { |
| 691 | { X, X, 0, {0, 0} }, /* none */ |
| 692 | { 0, 0, 0x1, {0x010000, 64 * 1024} }, |
| 693 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 694 | { X, X, 0x2, {0x000000, 128 * 1024} }, |
| 695 | { X, X, 0x3, {0x000000, 128 * 1024} }, |
| 696 | }; |
| 697 | |
| 698 | struct w25q_range w25x20_ranges[] = { |
| 699 | { X, X, 0, {0, 0} }, /* none */ |
| 700 | { 0, 0, 0x1, {0x030000, 64 * 1024} }, |
| 701 | { 0, 0, 0x2, {0x020000, 128 * 1024} }, |
| 702 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 703 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 704 | { 0, X, 0x3, {0x000000, 256 * 1024} }, |
| 705 | }; |
| 706 | |
David Hendricks | 470ca95 | 2010-08-13 14:01:53 -0700 | [diff] [blame] | 707 | struct w25q_range w25x40_ranges[] = { |
| 708 | { X, X, 0, {0, 0} }, /* none */ |
| 709 | { 0, 0, 0x1, {0x070000, 64 * 1024} }, |
| 710 | { 0, 0, 0x2, {0x060000, 128 * 1024} }, |
| 711 | { 0, 0, 0x3, {0x040000, 256 * 1024} }, |
| 712 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 713 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 714 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 715 | { 0, X, 0x4, {0x000000, 512 * 1024} }, |
David Hendricks | b389abb | 2016-06-17 16:47:00 -0700 | [diff] [blame] | 716 | { 0, X, 0x5, {0x000000, 512 * 1024} }, |
| 717 | { 0, X, 0x6, {0x000000, 512 * 1024} }, |
| 718 | { 0, X, 0x7, {0x000000, 512 * 1024} }, |
David Hendricks | 470ca95 | 2010-08-13 14:01:53 -0700 | [diff] [blame] | 719 | }; |
| 720 | |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 721 | struct w25q_range w25x80_ranges[] = { |
| 722 | { X, X, 0, {0, 0} }, /* none */ |
| 723 | { 0, 0, 0x1, {0x0F0000, 64 * 1024} }, |
| 724 | { 0, 0, 0x2, {0x0E0000, 128 * 1024} }, |
| 725 | { 0, 0, 0x3, {0x0C0000, 256 * 1024} }, |
| 726 | { 0, 0, 0x4, {0x080000, 512 * 1024} }, |
| 727 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 728 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 729 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 730 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
| 731 | { 0, X, 0x5, {0x000000, 1024 * 1024} }, |
| 732 | { 0, X, 0x6, {0x000000, 1024 * 1024} }, |
| 733 | { 0, X, 0x7, {0x000000, 1024 * 1024} }, |
| 734 | }; |
| 735 | |
Martin Roth | f3c3d5f | 2017-04-28 14:56:41 -0600 | [diff] [blame] | 736 | static struct w25q_range gd25q40_cmp0_ranges[] = { |
| 737 | { X, X, 0, {0, 0} }, /* None */ |
| 738 | { 0, 0, 0x1, {0x070000, 64 * 1024} }, |
| 739 | { 0, 0, 0x2, {0x060000, 128 * 1024} }, |
| 740 | { 0, 0, 0x3, {0x040000, 256 * 1024} }, |
| 741 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 742 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 743 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 744 | { 0, X, 0x4, {0x000000, 512 * 1024} }, /* All */ |
| 745 | { 0, X, 0x5, {0x000000, 512 * 1024} }, /* All */ |
| 746 | { 0, X, 0x6, {0x000000, 512 * 1024} }, /* All */ |
| 747 | { 0, X, 0x7, {0x000000, 512 * 1024} }, /* All */ |
| 748 | { 1, 0, 0x1, {0x07F000, 4 * 1024} }, |
| 749 | { 1, 0, 0x2, {0x07E000, 8 * 1024} }, |
| 750 | { 1, 0, 0x3, {0x07C000, 16 * 1024} }, |
| 751 | { 1, 0, 0x4, {0x078000, 32 * 1024} }, |
| 752 | { 1, 0, 0x5, {0x078000, 32 * 1024} }, |
| 753 | { 1, 0, 0x6, {0x078000, 32 * 1024} }, |
| 754 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 755 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 756 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 757 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 758 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 759 | { 1, 1, 0x6, {0x000000, 32 * 1024} }, |
| 760 | { 1, X, 0x7, {0x000000, 512 * 1024} }, /* All */ |
| 761 | }; |
| 762 | |
| 763 | static struct w25q_range gd25q40_cmp1_ranges[] = { |
| 764 | { X, X, 0x0, {0x000000, 512 * 1024} }, /* ALL */ |
| 765 | { 0, 0, 0x1, {0x000000, 448 * 1024} }, |
| 766 | { 0, 0, 0x2, {0x000000, 384 * 1024} }, |
| 767 | { 0, 0, 0x3, {0x000000, 256 * 1024} }, |
| 768 | |
| 769 | { 0, 1, 0x1, {0x010000, 448 * 1024} }, |
| 770 | { 0, 1, 0x2, {0x020000, 384 * 1024} }, |
| 771 | { 0, 1, 0x3, {0x040000, 256 * 1024} }, |
| 772 | |
| 773 | { 0, X, 0x4, {0x000000, 0} }, /* None */ |
| 774 | { 0, X, 0x5, {0x000000, 0} }, /* None */ |
| 775 | { 0, X, 0x6, {0x000000, 0} }, /* None */ |
| 776 | { 0, X, 0x7, {0x000000, 0} }, /* None */ |
| 777 | |
| 778 | { 1, 0, 0x1, {0x000000, 508 * 1024} }, |
| 779 | { 1, 0, 0x2, {0x000000, 504 * 1024} }, |
| 780 | { 1, 0, 0x3, {0x000000, 496 * 1024} }, |
| 781 | { 1, 0, 0x4, {0x000000, 480 * 1024} }, |
| 782 | { 1, 0, 0x5, {0x000000, 480 * 1024} }, |
| 783 | { 1, 0, 0x6, {0x000000, 480 * 1024} }, |
| 784 | |
| 785 | { 1, 1, 0x1, {0x001000, 508 * 1024} }, |
| 786 | { 1, 1, 0x2, {0x002000, 504 * 1024} }, |
| 787 | { 1, 1, 0x3, {0x004000, 496 * 1024} }, |
| 788 | { 1, 1, 0x4, {0x008000, 480 * 1024} }, |
| 789 | { 1, 1, 0x5, {0x008000, 480 * 1024} }, |
| 790 | { 1, 1, 0x6, {0x008000, 480 * 1024} }, |
| 791 | |
| 792 | { 1, X, 0x7, {0x000000, 0} }, /* None */ |
| 793 | }; |
| 794 | |
Shawn Nematbakhsh | 9e8ef49 | 2012-09-01 21:58:03 -0700 | [diff] [blame] | 795 | static struct w25q_range gd25q64_ranges[] = { |
| 796 | { X, X, 0, {0, 0} }, /* none */ |
| 797 | { 0, 0, 0x1, {0x7e0000, 128 * 1024} }, |
| 798 | { 0, 0, 0x2, {0x7c0000, 256 * 1024} }, |
| 799 | { 0, 0, 0x3, {0x780000, 512 * 1024} }, |
| 800 | { 0, 0, 0x4, {0x700000, 1024 * 1024} }, |
| 801 | { 0, 0, 0x5, {0x600000, 2048 * 1024} }, |
| 802 | { 0, 0, 0x6, {0x400000, 4096 * 1024} }, |
| 803 | |
| 804 | { 0, 1, 0x1, {0x000000, 128 * 1024} }, |
| 805 | { 0, 1, 0x2, {0x000000, 256 * 1024} }, |
| 806 | { 0, 1, 0x3, {0x000000, 512 * 1024} }, |
| 807 | { 0, 1, 0x4, {0x000000, 1024 * 1024} }, |
| 808 | { 0, 1, 0x5, {0x000000, 2048 * 1024} }, |
| 809 | { 0, 1, 0x6, {0x000000, 4096 * 1024} }, |
| 810 | { X, X, 0x7, {0x000000, 8192 * 1024} }, |
| 811 | |
| 812 | { 1, 0, 0x1, {0x7ff000, 4 * 1024} }, |
| 813 | { 1, 0, 0x2, {0x7fe000, 8 * 1024} }, |
| 814 | { 1, 0, 0x3, {0x7fc000, 16 * 1024} }, |
| 815 | { 1, 0, 0x4, {0x7f8000, 32 * 1024} }, |
| 816 | { 1, 0, 0x5, {0x7f8000, 32 * 1024} }, |
| 817 | { 1, 0, 0x6, {0x7f8000, 32 * 1024} }, |
| 818 | |
| 819 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 820 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 821 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 822 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 823 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 824 | { 1, 1, 0x6, {0x000000, 32 * 1024} }, |
| 825 | }; |
| 826 | |
Louis Yung-Chieh Lo | c8ec715 | 2012-09-17 17:38:35 +0800 | [diff] [blame] | 827 | static struct w25q_range a25l040_ranges[] = { |
| 828 | { X, X, 0x0, {0, 0} }, /* none */ |
| 829 | { X, X, 0x1, {0x70000, 64 * 1024} }, |
| 830 | { X, X, 0x2, {0x60000, 128 * 1024} }, |
| 831 | { X, X, 0x3, {0x40000, 256 * 1024} }, |
| 832 | { X, X, 0x4, {0x00000, 512 * 1024} }, |
| 833 | { X, X, 0x5, {0x00000, 512 * 1024} }, |
| 834 | { X, X, 0x6, {0x00000, 512 * 1024} }, |
| 835 | { X, X, 0x7, {0x00000, 512 * 1024} }, |
| 836 | }; |
| 837 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 838 | static uint8_t do_read_status(const struct flashctx *flash) |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 839 | { |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 840 | if (flash->chip->read_status) |
| 841 | return flash->chip->read_status(flash); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 842 | else |
| 843 | return spi_read_status_register(flash); |
| 844 | } |
| 845 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 846 | static int do_write_status(const struct flashctx *flash, int status) |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 847 | { |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 848 | if (flash->chip->write_status) |
| 849 | return flash->chip->write_status(flash, status); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 850 | else |
| 851 | return spi_write_status_register(flash, status); |
| 852 | } |
| 853 | |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 854 | /* FIXME: Move to spi25.c if it's a JEDEC standard opcode */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 855 | static uint8_t w25q_read_status_register_2(const struct flashctx *flash) |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 856 | { |
| 857 | static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x35 }; |
| 858 | unsigned char readarr[2]; |
| 859 | int ret; |
| 860 | |
| 861 | /* Read Status Register */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 862 | ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 863 | if (ret) { |
| 864 | /* |
| 865 | * FIXME: make this a benign failure for now in case we are |
| 866 | * unable to execute the opcode |
| 867 | */ |
| 868 | msg_cdbg("RDSR2 failed!\n"); |
| 869 | readarr[0] = 0x00; |
| 870 | } |
| 871 | |
| 872 | return readarr[0]; |
| 873 | } |
| 874 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 875 | /* Given a flash chip, this function returns its range table. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 876 | static int w25_range_table(const struct flashctx *flash, |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 877 | struct w25q_range **w25q_ranges, |
| 878 | int *num_entries) |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 879 | { |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 880 | *w25q_ranges = 0; |
| 881 | *num_entries = 0; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 882 | |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 883 | switch (flash->chip->manufacture_id) { |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 884 | case WINBOND_NEX_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 885 | switch(flash->chip->model_id) { |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 886 | case WINBOND_NEX_W25X10: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 887 | *w25q_ranges = w25x10_ranges; |
| 888 | *num_entries = ARRAY_SIZE(w25x10_ranges); |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 889 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 890 | case WINBOND_NEX_W25X20: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 891 | *w25q_ranges = w25x20_ranges; |
| 892 | *num_entries = ARRAY_SIZE(w25x20_ranges); |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 893 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 894 | case WINBOND_NEX_W25X40: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 895 | *w25q_ranges = w25x40_ranges; |
| 896 | *num_entries = ARRAY_SIZE(w25x40_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 897 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 898 | case WINBOND_NEX_W25X80: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 899 | *w25q_ranges = w25x80_ranges; |
| 900 | *num_entries = ARRAY_SIZE(w25x80_ranges); |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 901 | break; |
Patrick Georgi | cc04a45 | 2017-02-06 12:14:43 +0100 | [diff] [blame] | 902 | case WINBOND_NEX_W25Q80_V: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 903 | *w25q_ranges = w25q80_ranges; |
| 904 | *num_entries = ARRAY_SIZE(w25q80_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 905 | break; |
Patrick Georgi | cc04a45 | 2017-02-06 12:14:43 +0100 | [diff] [blame] | 906 | case WINBOND_NEX_W25Q16_V: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 907 | *w25q_ranges = w25q16_ranges; |
| 908 | *num_entries = ARRAY_SIZE(w25q16_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 909 | break; |
Patrick Georgi | cc04a45 | 2017-02-06 12:14:43 +0100 | [diff] [blame] | 910 | case WINBOND_NEX_W25Q32_V: |
| 911 | case WINBOND_NEX_W25Q32_W: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 912 | *w25q_ranges = w25q32_ranges; |
| 913 | *num_entries = ARRAY_SIZE(w25q32_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 914 | break; |
Patrick Georgi | cc04a45 | 2017-02-06 12:14:43 +0100 | [diff] [blame] | 915 | case WINBOND_NEX_W25Q64_V: |
| 916 | case WINBOND_NEX_W25Q64_W: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 917 | *w25q_ranges = w25q64_ranges; |
| 918 | *num_entries = ARRAY_SIZE(w25q64_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 919 | break; |
Martin Roth | ee8dcf9 | 2017-05-10 19:16:19 -0600 | [diff] [blame] | 920 | case WINBOND_NEX_W25Q128J: |
Patrick Georgi | cc04a45 | 2017-02-06 12:14:43 +0100 | [diff] [blame] | 921 | case WINBOND_NEX_W25Q128_V: |
| 922 | case WINBOND_NEX_W25Q128_W: |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 923 | if (w25q_read_status_register_2(flash) & (1 << 6)) { |
Duncan Laurie | ed32d7b | 2015-05-27 11:28:18 -0700 | [diff] [blame] | 924 | /* CMP == 1 */ |
| 925 | *w25q_ranges = w25rq128_cmp1_ranges; |
| 926 | *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges); |
| 927 | } else { |
| 928 | /* CMP == 0 */ |
| 929 | *w25q_ranges = w25rq128_cmp0_ranges; |
| 930 | *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges); |
| 931 | } |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 932 | break; |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 933 | case WINBOND_NEX_W25Q256JV: |
| 934 | if (w25q_read_status_register_2(flash) & (1 << 6)) { |
| 935 | /* CMP == 1 */ |
| 936 | *w25q_ranges = w25rq256_cmp1_ranges; |
| 937 | *num_entries = ARRAY_SIZE(w25rq256_cmp1_ranges); |
| 938 | } else { |
| 939 | /* CMP == 0 */ |
| 940 | *w25q_ranges = w25rq256_cmp0_ranges; |
| 941 | *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges); |
| 942 | } |
| 943 | break; |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 944 | default: |
| 945 | msg_cerr("%s() %d: WINBOND flash chip mismatch (0x%04x)" |
| 946 | ", aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 947 | flash->chip->model_id); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 948 | return -1; |
| 949 | } |
David Hendricks | 2c4a76c | 2010-06-28 14:00:43 -0700 | [diff] [blame] | 950 | break; |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 951 | case EON_ID_NOPREFIX: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 952 | switch (flash->chip->model_id) { |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 953 | case EON_EN25F40: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 954 | *w25q_ranges = en25f40_ranges; |
| 955 | *num_entries = ARRAY_SIZE(en25f40_ranges); |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 956 | break; |
David Hendricks | e185bf2 | 2011-05-24 15:34:18 -0700 | [diff] [blame] | 957 | case EON_EN25Q40: |
| 958 | *w25q_ranges = en25q40_ranges; |
| 959 | *num_entries = ARRAY_SIZE(en25q40_ranges); |
| 960 | break; |
| 961 | case EON_EN25Q80: |
| 962 | *w25q_ranges = en25q80_ranges; |
| 963 | *num_entries = ARRAY_SIZE(en25q80_ranges); |
| 964 | break; |
| 965 | case EON_EN25Q32: |
| 966 | *w25q_ranges = en25q32_ranges; |
| 967 | *num_entries = ARRAY_SIZE(en25q32_ranges); |
| 968 | break; |
| 969 | case EON_EN25Q64: |
| 970 | *w25q_ranges = en25q64_ranges; |
| 971 | *num_entries = ARRAY_SIZE(en25q64_ranges); |
| 972 | break; |
| 973 | case EON_EN25Q128: |
| 974 | *w25q_ranges = en25q128_ranges; |
| 975 | *num_entries = ARRAY_SIZE(en25q128_ranges); |
| 976 | break; |
Marc Jones | b2f9002 | 2014-04-29 17:37:23 -0600 | [diff] [blame] | 977 | case EON_EN25S64: |
| 978 | *w25q_ranges = en25s64_ranges; |
| 979 | *num_entries = ARRAY_SIZE(en25s64_ranges); |
| 980 | break; |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 981 | default: |
| 982 | msg_cerr("%s():%d: EON flash chip mismatch (0x%04x)" |
| 983 | ", aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 984 | flash->chip->model_id); |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 985 | return -1; |
| 986 | } |
| 987 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 988 | case MACRONIX_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 989 | switch (flash->chip->model_id) { |
David Hendricks | f8f00c7 | 2011-02-01 12:39:46 -0800 | [diff] [blame] | 990 | case MACRONIX_MX25L1005: |
| 991 | *w25q_ranges = mx25l1005_ranges; |
| 992 | *num_entries = ARRAY_SIZE(mx25l1005_ranges); |
| 993 | break; |
| 994 | case MACRONIX_MX25L2005: |
| 995 | *w25q_ranges = mx25l2005_ranges; |
| 996 | *num_entries = ARRAY_SIZE(mx25l2005_ranges); |
| 997 | break; |
| 998 | case MACRONIX_MX25L4005: |
| 999 | *w25q_ranges = mx25l4005_ranges; |
| 1000 | *num_entries = ARRAY_SIZE(mx25l4005_ranges); |
| 1001 | break; |
| 1002 | case MACRONIX_MX25L8005: |
| 1003 | *w25q_ranges = mx25l8005_ranges; |
| 1004 | *num_entries = ARRAY_SIZE(mx25l8005_ranges); |
| 1005 | break; |
| 1006 | case MACRONIX_MX25L1605: |
| 1007 | /* FIXME: MX25L1605 and MX25L1605D have different write |
| 1008 | * protection capabilities, but share IDs */ |
| 1009 | *w25q_ranges = mx25l1605d_ranges; |
| 1010 | *num_entries = ARRAY_SIZE(mx25l1605d_ranges); |
| 1011 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 1012 | case MACRONIX_MX25L3205: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1013 | *w25q_ranges = mx25l3205d_ranges; |
| 1014 | *num_entries = ARRAY_SIZE(mx25l3205d_ranges); |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 1015 | break; |
Vincent Palatin | 87e092a | 2013-02-28 15:46:14 -0800 | [diff] [blame] | 1016 | case MACRONIX_MX25U3235E: |
| 1017 | *w25q_ranges = mx25u3235e_ranges; |
| 1018 | *num_entries = ARRAY_SIZE(mx25u3235e_ranges); |
| 1019 | break; |
Jongpil | 66a9649 | 2014-08-14 17:59:06 +0900 | [diff] [blame] | 1020 | case MACRONIX_MX25U6435E: |
| 1021 | *w25q_ranges = mx25u6435e_ranges; |
| 1022 | *num_entries = ARRAY_SIZE(mx25u6435e_ranges); |
| 1023 | break; |
Alex Lu | 831c609 | 2017-11-02 23:19:34 -0700 | [diff] [blame] | 1024 | case MACRONIX_MX25U12835F: |
| 1025 | *w25q_ranges = mx25u12835f_ranges; |
| 1026 | *num_entries = ARRAY_SIZE(mx25u12835f_ranges); |
| 1027 | break; |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 1028 | default: |
| 1029 | msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)" |
| 1030 | ", aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1031 | flash->chip->model_id); |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 1032 | return -1; |
| 1033 | } |
| 1034 | break; |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 1035 | case ST_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1036 | switch(flash->chip->model_id) { |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 1037 | case ST_N25Q064__1E: |
| 1038 | case ST_N25Q064__3E: |
| 1039 | *w25q_ranges = n25q064_ranges; |
| 1040 | *num_entries = ARRAY_SIZE(n25q064_ranges); |
| 1041 | break; |
| 1042 | default: |
| 1043 | msg_cerr("%s() %d: Micron flash chip mismatch" |
| 1044 | " (0x%04x), aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1045 | flash->chip->model_id); |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 1046 | return -1; |
| 1047 | } |
| 1048 | break; |
Bryan Freed | 9a0051f | 2012-05-22 16:06:09 -0700 | [diff] [blame] | 1049 | case GIGADEVICE_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1050 | switch(flash->chip->model_id) { |
Bryan Freed | 9a0051f | 2012-05-22 16:06:09 -0700 | [diff] [blame] | 1051 | case GIGADEVICE_GD25LQ32: |
| 1052 | *w25q_ranges = w25q32_ranges; |
| 1053 | *num_entries = ARRAY_SIZE(w25q32_ranges); |
| 1054 | break; |
Martin Roth | f3c3d5f | 2017-04-28 14:56:41 -0600 | [diff] [blame] | 1055 | case GIGADEVICE_GD25Q40: |
| 1056 | if (w25q_read_status_register_2(flash) & (1 << 6)) { |
| 1057 | /* CMP == 1 */ |
| 1058 | *w25q_ranges = gd25q40_cmp1_ranges; |
| 1059 | *num_entries = ARRAY_SIZE(gd25q40_cmp1_ranges); |
| 1060 | } else { |
| 1061 | *w25q_ranges = gd25q40_cmp0_ranges; |
| 1062 | *num_entries = ARRAY_SIZE(gd25q40_cmp0_ranges); |
| 1063 | } |
| 1064 | break; |
Shawn Nematbakhsh | 9e8ef49 | 2012-09-01 21:58:03 -0700 | [diff] [blame] | 1065 | case GIGADEVICE_GD25Q64: |
Marc Jones | b18734f | 2014-04-03 16:19:47 -0600 | [diff] [blame] | 1066 | case GIGADEVICE_GD25LQ64: |
Shawn Nematbakhsh | 9e8ef49 | 2012-09-01 21:58:03 -0700 | [diff] [blame] | 1067 | *w25q_ranges = gd25q64_ranges; |
| 1068 | *num_entries = ARRAY_SIZE(gd25q64_ranges); |
| 1069 | break; |
Martin Roth | 1fd87ed | 2017-02-27 20:50:50 -0700 | [diff] [blame] | 1070 | case GIGADEVICE_GD25Q128: |
Aaron Durbin | 6c957d7 | 2018-08-20 09:31:01 -0600 | [diff] [blame] | 1071 | case GIGADEVICE_GD25LQ128CD: |
Martin Roth | 1fd87ed | 2017-02-27 20:50:50 -0700 | [diff] [blame] | 1072 | if (w25q_read_status_register_2(flash) & (1 << 6)) { |
| 1073 | /* CMP == 1 */ |
| 1074 | *w25q_ranges = w25rq128_cmp1_ranges; |
| 1075 | *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges); |
| 1076 | } else { |
| 1077 | /* CMP == 0 */ |
| 1078 | *w25q_ranges = w25rq128_cmp0_ranges; |
| 1079 | *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges); |
| 1080 | } |
| 1081 | break; |
Bryan Freed | 9a0051f | 2012-05-22 16:06:09 -0700 | [diff] [blame] | 1082 | default: |
| 1083 | msg_cerr("%s() %d: GigaDevice flash chip mismatch" |
| 1084 | " (0x%04x), aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1085 | flash->chip->model_id); |
Bryan Freed | 9a0051f | 2012-05-22 16:06:09 -0700 | [diff] [blame] | 1086 | return -1; |
| 1087 | } |
| 1088 | break; |
Louis Yung-Chieh Lo | c8ec715 | 2012-09-17 17:38:35 +0800 | [diff] [blame] | 1089 | case AMIC_ID_NOPREFIX: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1090 | switch(flash->chip->model_id) { |
Louis Yung-Chieh Lo | c8ec715 | 2012-09-17 17:38:35 +0800 | [diff] [blame] | 1091 | case AMIC_A25L040: |
| 1092 | *w25q_ranges = a25l040_ranges; |
| 1093 | *num_entries = ARRAY_SIZE(a25l040_ranges); |
| 1094 | break; |
| 1095 | default: |
| 1096 | msg_cerr("%s() %d: AMIC flash chip mismatch" |
| 1097 | " (0x%04x), aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1098 | flash->chip->model_id); |
Louis Yung-Chieh Lo | c8ec715 | 2012-09-17 17:38:35 +0800 | [diff] [blame] | 1099 | return -1; |
| 1100 | } |
| 1101 | break; |
Furquan Shaikh | b4df8ef | 2017-01-05 15:05:35 -0800 | [diff] [blame] | 1102 | case ATMEL_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1103 | switch(flash->chip->model_id) { |
Furquan Shaikh | b4df8ef | 2017-01-05 15:05:35 -0800 | [diff] [blame] | 1104 | case ATMEL_AT25SL128A: |
| 1105 | if (w25q_read_status_register_2(flash) & (1 << 6)) { |
| 1106 | /* CMP == 1 */ |
| 1107 | *w25q_ranges = w25rq128_cmp1_ranges; |
| 1108 | *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges); |
| 1109 | } else { |
| 1110 | /* CMP == 0 */ |
| 1111 | *w25q_ranges = w25rq128_cmp0_ranges; |
| 1112 | *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges); |
| 1113 | } |
| 1114 | break; |
| 1115 | default: |
| 1116 | msg_cerr("%s() %d: Atmel flash chip mismatch" |
| 1117 | " (0x%04x), aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1118 | flash->chip->model_id); |
Furquan Shaikh | b4df8ef | 2017-01-05 15:05:35 -0800 | [diff] [blame] | 1119 | return -1; |
| 1120 | } |
| 1121 | break; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1122 | default: |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 1123 | msg_cerr("%s: flash vendor (0x%x) not found, aborting\n", |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 1124 | __func__, flash->chip->manufacture_id); |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1125 | return -1; |
| 1126 | } |
| 1127 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1128 | return 0; |
| 1129 | } |
| 1130 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1131 | int w25_range_to_status(const struct flashctx *flash, |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1132 | unsigned int start, unsigned int len, |
| 1133 | struct w25q_status *status) |
| 1134 | { |
| 1135 | struct w25q_range *w25q_ranges; |
| 1136 | int i, range_found = 0; |
| 1137 | int num_entries; |
| 1138 | |
| 1139 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) return -1; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1140 | for (i = 0; i < num_entries; i++) { |
| 1141 | struct wp_range *r = &w25q_ranges[i].range; |
| 1142 | |
| 1143 | msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n", |
| 1144 | start, len, r->start, r->len); |
| 1145 | if ((start == r->start) && (len == r->len)) { |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 1146 | status->bp0 = w25q_ranges[i].bp & 1; |
| 1147 | status->bp1 = w25q_ranges[i].bp >> 1; |
| 1148 | status->bp2 = w25q_ranges[i].bp >> 2; |
| 1149 | status->tb = w25q_ranges[i].tb; |
| 1150 | status->sec = w25q_ranges[i].sec; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1151 | |
| 1152 | range_found = 1; |
| 1153 | break; |
| 1154 | } |
| 1155 | } |
| 1156 | |
| 1157 | if (!range_found) { |
| 1158 | msg_cerr("matching range not found\n"); |
| 1159 | return -1; |
| 1160 | } |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 1161 | return 0; |
| 1162 | } |
| 1163 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1164 | int w25_status_to_range(const struct flashctx *flash, |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1165 | const struct w25q_status *status, |
| 1166 | unsigned int *start, unsigned int *len) |
| 1167 | { |
| 1168 | struct w25q_range *w25q_ranges; |
| 1169 | int i, status_found = 0; |
| 1170 | int num_entries; |
| 1171 | |
| 1172 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) return -1; |
| 1173 | for (i = 0; i < num_entries; i++) { |
| 1174 | int bp; |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 1175 | int table_bp, table_tb, table_sec; |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1176 | |
| 1177 | bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2); |
| 1178 | msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x / 0x%x 0x%x\n", |
| 1179 | bp, w25q_ranges[i].bp, |
| 1180 | status->tb, w25q_ranges[i].tb, |
| 1181 | status->sec, w25q_ranges[i].sec); |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 1182 | table_bp = w25q_ranges[i].bp; |
| 1183 | table_tb = w25q_ranges[i].tb; |
| 1184 | table_sec = w25q_ranges[i].sec; |
| 1185 | if ((bp == table_bp || table_bp == X) && |
| 1186 | (status->tb == table_tb || table_tb == X) && |
| 1187 | (status->sec == table_sec || table_sec == X)) { |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1188 | *start = w25q_ranges[i].range.start; |
| 1189 | *len = w25q_ranges[i].range.len; |
| 1190 | |
| 1191 | status_found = 1; |
| 1192 | break; |
| 1193 | } |
| 1194 | } |
| 1195 | |
| 1196 | if (!status_found) { |
| 1197 | msg_cerr("matching status not found\n"); |
| 1198 | return -1; |
| 1199 | } |
| 1200 | return 0; |
| 1201 | } |
| 1202 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1203 | /* Given a [start, len], this function calls w25_range_to_status() to convert |
| 1204 | * it to flash-chip-specific range bits, then sets into status register. |
| 1205 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1206 | static int w25_set_range(const struct flashctx *flash, |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 1207 | unsigned int start, unsigned int len) |
| 1208 | { |
| 1209 | struct w25q_status status; |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1210 | int tmp = 0; |
| 1211 | int expected = 0; |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 1212 | |
| 1213 | memset(&status, 0, sizeof(status)); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1214 | tmp = do_read_status(flash); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 1215 | memcpy(&status, &tmp, 1); |
| 1216 | msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp); |
| 1217 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1218 | if (w25_range_to_status(flash, start, len, &status)) return -1; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1219 | |
| 1220 | msg_cdbg("status.busy: %x\n", status.busy); |
| 1221 | msg_cdbg("status.wel: %x\n", status.wel); |
| 1222 | msg_cdbg("status.bp0: %x\n", status.bp0); |
| 1223 | msg_cdbg("status.bp1: %x\n", status.bp1); |
| 1224 | msg_cdbg("status.bp2: %x\n", status.bp2); |
| 1225 | msg_cdbg("status.tb: %x\n", status.tb); |
| 1226 | msg_cdbg("status.sec: %x\n", status.sec); |
| 1227 | msg_cdbg("status.srp0: %x\n", status.srp0); |
| 1228 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1229 | memcpy(&expected, &status, sizeof(status)); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1230 | do_write_status(flash, expected); |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1231 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1232 | tmp = do_read_status(flash); |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1233 | msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp); |
| 1234 | if ((tmp & MASK_WP_AREA) == (expected & MASK_WP_AREA)) { |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1235 | return 0; |
| 1236 | } else { |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 1237 | msg_cerr("expected=0x%02x, but actual=0x%02x.\n", |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1238 | expected, tmp); |
| 1239 | return 1; |
| 1240 | } |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1241 | } |
| 1242 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1243 | /* Print out the current status register value with human-readable text. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1244 | static int w25_wp_status(const struct flashctx *flash) |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1245 | { |
| 1246 | struct w25q_status status; |
| 1247 | int tmp; |
David Hendricks | ce8ded3 | 2010-10-08 11:23:38 -0700 | [diff] [blame] | 1248 | unsigned int start, len; |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1249 | int ret = 0; |
| 1250 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1251 | memset(&status, 0, sizeof(status)); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1252 | tmp = do_read_status(flash); |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1253 | memcpy(&status, &tmp, 1); |
| 1254 | msg_cinfo("WP: status: 0x%02x\n", tmp); |
| 1255 | msg_cinfo("WP: status.srp0: %x\n", status.srp0); |
| 1256 | msg_cinfo("WP: write protect is %s.\n", |
| 1257 | status.srp0 ? "enabled" : "disabled"); |
| 1258 | |
| 1259 | msg_cinfo("WP: write protect range: "); |
| 1260 | if (w25_status_to_range(flash, &status, &start, &len)) { |
| 1261 | msg_cinfo("(cannot resolve the range)\n"); |
| 1262 | ret = -1; |
| 1263 | } else { |
| 1264 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 1265 | } |
| 1266 | |
| 1267 | return ret; |
| 1268 | } |
| 1269 | |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 1270 | static int w25q_large_range_to_status(const struct flashctx *flash, |
| 1271 | unsigned int start, unsigned int len, |
| 1272 | struct w25q_status_large *status) |
| 1273 | { |
| 1274 | struct w25q_range *w25q_ranges; |
| 1275 | int i, range_found = 0; |
| 1276 | int num_entries; |
| 1277 | |
| 1278 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) |
| 1279 | return -1; |
| 1280 | for (i = 0; i < num_entries; i++) { |
| 1281 | struct wp_range *r = &w25q_ranges[i].range; |
| 1282 | |
| 1283 | msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n", |
| 1284 | start, len, r->start, r->len); |
| 1285 | if ((start == r->start) && (len == r->len)) { |
| 1286 | status->bp0 = w25q_ranges[i].bp & 1; |
| 1287 | status->bp1 = w25q_ranges[i].bp >> 1; |
| 1288 | status->bp2 = w25q_ranges[i].bp >> 2; |
| 1289 | status->bp3 = w25q_ranges[i].bp >> 3; |
| 1290 | status->tb = w25q_ranges[i].tb; |
| 1291 | |
| 1292 | range_found = 1; |
| 1293 | break; |
| 1294 | } |
| 1295 | } |
| 1296 | |
| 1297 | if (!range_found) { |
| 1298 | msg_cerr("matching range not found\n"); |
| 1299 | return -1; |
| 1300 | } |
| 1301 | return 0; |
| 1302 | } |
| 1303 | |
| 1304 | static int w25_large_status_to_range(const struct flashctx *flash, |
| 1305 | const struct w25q_status_large *status, |
| 1306 | unsigned int *start, unsigned int *len) |
| 1307 | { |
| 1308 | struct w25q_range *w25q_ranges; |
| 1309 | int i, status_found = 0; |
| 1310 | int num_entries; |
| 1311 | |
| 1312 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) |
| 1313 | return -1; |
| 1314 | for (i = 0; i < num_entries; i++) { |
| 1315 | int bp; |
| 1316 | int table_bp, table_tb; |
| 1317 | |
| 1318 | bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2) | |
| 1319 | (status->bp3 << 3); |
| 1320 | msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x\n", |
| 1321 | bp, w25q_ranges[i].bp, |
| 1322 | status->tb, w25q_ranges[i].tb); |
| 1323 | table_bp = w25q_ranges[i].bp; |
| 1324 | table_tb = w25q_ranges[i].tb; |
| 1325 | if ((bp == table_bp || table_bp == X) && |
| 1326 | (status->tb == table_tb || table_tb == X)) { |
| 1327 | *start = w25q_ranges[i].range.start; |
| 1328 | *len = w25q_ranges[i].range.len; |
| 1329 | |
| 1330 | status_found = 1; |
| 1331 | break; |
| 1332 | } |
| 1333 | } |
| 1334 | |
| 1335 | if (!status_found) { |
| 1336 | msg_cerr("matching status not found\n"); |
| 1337 | return -1; |
| 1338 | } |
| 1339 | return 0; |
| 1340 | } |
| 1341 | |
| 1342 | /* Given a [start, len], this function calls w25_range_to_status() to convert |
| 1343 | * it to flash-chip-specific range bits, then sets into status register. |
| 1344 | * Returns 0 if successful, -1 on error, and 1 if reading back was different. |
| 1345 | */ |
| 1346 | static int w25q_large_set_range(const struct flashctx *flash, |
| 1347 | unsigned int start, unsigned int len) |
| 1348 | { |
| 1349 | struct w25q_status_large status; |
| 1350 | int tmp; |
| 1351 | int expected = 0; |
| 1352 | |
| 1353 | memset(&status, 0, sizeof(status)); |
| 1354 | tmp = do_read_status(flash); |
| 1355 | memcpy(&status, &tmp, 1); |
| 1356 | msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp); |
| 1357 | |
| 1358 | if (w25q_large_range_to_status(flash, start, len, &status)) |
| 1359 | return -1; |
| 1360 | |
| 1361 | msg_cdbg("status.busy: %x\n", status.busy); |
| 1362 | msg_cdbg("status.wel: %x\n", status.wel); |
| 1363 | msg_cdbg("status.bp0: %x\n", status.bp0); |
| 1364 | msg_cdbg("status.bp1: %x\n", status.bp1); |
| 1365 | msg_cdbg("status.bp2: %x\n", status.bp2); |
| 1366 | msg_cdbg("status.bp3: %x\n", status.bp3); |
| 1367 | msg_cdbg("status.tb: %x\n", status.tb); |
| 1368 | msg_cdbg("status.srp0: %x\n", status.srp0); |
| 1369 | |
| 1370 | memcpy(&expected, &status, sizeof(status)); |
| 1371 | do_write_status(flash, expected); |
| 1372 | |
| 1373 | tmp = do_read_status(flash); |
| 1374 | msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp); |
| 1375 | if ((tmp & MASK_WP_AREA_LARGE) == (expected & MASK_WP_AREA_LARGE)) { |
| 1376 | return 0; |
| 1377 | } else { |
| 1378 | msg_cerr("expected=0x%02x, but actual=0x%02x.\n", |
| 1379 | expected, tmp); |
| 1380 | return 1; |
| 1381 | } |
| 1382 | } |
| 1383 | |
| 1384 | static int w25q_large_wp_status(const struct flashctx *flash) |
| 1385 | { |
| 1386 | struct w25q_status_large sr1; |
| 1387 | struct w25q_status_2 sr2; |
| 1388 | uint8_t tmp[2]; |
| 1389 | unsigned int start, len; |
| 1390 | int ret = 0; |
| 1391 | |
| 1392 | memset(&sr1, 0, sizeof(sr1)); |
| 1393 | tmp[0] = do_read_status(flash); |
| 1394 | memcpy(&sr1, &tmp[0], 1); |
| 1395 | |
| 1396 | memset(&sr2, 0, sizeof(sr2)); |
| 1397 | tmp[1] = w25q_read_status_register_2(flash); |
| 1398 | memcpy(&sr2, &tmp[1], 1); |
| 1399 | |
| 1400 | msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]); |
| 1401 | msg_cinfo("WP: status.srp0: %x\n", sr1.srp0); |
| 1402 | msg_cinfo("WP: status.srp1: %x\n", sr2.srp1); |
| 1403 | msg_cinfo("WP: write protect is %s.\n", |
| 1404 | (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled"); |
| 1405 | |
| 1406 | msg_cinfo("WP: write protect range: "); |
| 1407 | if (w25_large_status_to_range(flash, &sr1, &start, &len)) { |
| 1408 | msg_cinfo("(cannot resolve the range)\n"); |
| 1409 | ret = -1; |
| 1410 | } else { |
| 1411 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 1412 | } |
| 1413 | |
| 1414 | return ret; |
| 1415 | } |
| 1416 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1417 | /* Set/clear the SRP0 bit in the status register. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1418 | static int w25_set_srp0(const struct flashctx *flash, int enable) |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1419 | { |
| 1420 | struct w25q_status status; |
| 1421 | int tmp = 0; |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1422 | int expected = 0; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1423 | |
| 1424 | memset(&status, 0, sizeof(status)); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1425 | tmp = do_read_status(flash); |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1426 | /* FIXME: this is NOT endian-free copy. */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1427 | memcpy(&status, &tmp, 1); |
| 1428 | msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp); |
| 1429 | |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1430 | status.srp0 = enable ? 1 : 0; |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1431 | memcpy(&expected, &status, sizeof(status)); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1432 | do_write_status(flash, expected); |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1433 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1434 | tmp = do_read_status(flash); |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 1435 | msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp); |
| 1436 | if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA)) |
| 1437 | return 1; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1438 | |
| 1439 | return 0; |
| 1440 | } |
| 1441 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1442 | static int w25_enable_writeprotect(const struct flashctx *flash, |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1443 | enum wp_mode wp_mode) |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1444 | { |
| 1445 | int ret; |
| 1446 | |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1447 | switch (wp_mode) { |
| 1448 | case WP_MODE_HARDWARE: |
| 1449 | ret = w25_set_srp0(flash, 1); |
| 1450 | break; |
| 1451 | default: |
| 1452 | msg_cerr("%s(): unsupported write-protect mode\n", __func__); |
| 1453 | return 1; |
| 1454 | } |
| 1455 | |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 1456 | if (ret) |
| 1457 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1458 | return ret; |
| 1459 | } |
| 1460 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1461 | static int w25_disable_writeprotect(const struct flashctx *flash) |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1462 | { |
| 1463 | int ret; |
| 1464 | |
| 1465 | ret = w25_set_srp0(flash, 0); |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 1466 | if (ret) |
| 1467 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1468 | return ret; |
| 1469 | } |
| 1470 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1471 | static int w25_list_ranges(const struct flashctx *flash) |
David Hendricks | 0f7f538 | 2011-02-11 18:12:31 -0800 | [diff] [blame] | 1472 | { |
| 1473 | struct w25q_range *w25q_ranges; |
| 1474 | int i, num_entries; |
| 1475 | |
| 1476 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) return -1; |
| 1477 | for (i = 0; i < num_entries; i++) { |
| 1478 | msg_cinfo("start: 0x%06x, length: 0x%06x\n", |
| 1479 | w25q_ranges[i].range.start, |
| 1480 | w25q_ranges[i].range.len); |
| 1481 | } |
| 1482 | |
| 1483 | return 0; |
| 1484 | } |
| 1485 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1486 | static int w25q_wp_status(const struct flashctx *flash) |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1487 | { |
| 1488 | struct w25q_status sr1; |
| 1489 | struct w25q_status_2 sr2; |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1490 | uint8_t tmp[2]; |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1491 | unsigned int start, len; |
| 1492 | int ret = 0; |
| 1493 | |
| 1494 | memset(&sr1, 0, sizeof(sr1)); |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1495 | tmp[0] = do_read_status(flash); |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1496 | memcpy(&sr1, &tmp[0], 1); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1497 | |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1498 | memset(&sr2, 0, sizeof(sr2)); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1499 | tmp[1] = w25q_read_status_register_2(flash); |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1500 | memcpy(&sr2, &tmp[1], 1); |
| 1501 | |
| 1502 | msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1503 | msg_cinfo("WP: status.srp0: %x\n", sr1.srp0); |
| 1504 | msg_cinfo("WP: status.srp1: %x\n", sr2.srp1); |
| 1505 | msg_cinfo("WP: write protect is %s.\n", |
| 1506 | (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled"); |
| 1507 | |
| 1508 | msg_cinfo("WP: write protect range: "); |
| 1509 | if (w25_status_to_range(flash, &sr1, &start, &len)) { |
| 1510 | msg_cinfo("(cannot resolve the range)\n"); |
| 1511 | ret = -1; |
| 1512 | } else { |
| 1513 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 1514 | } |
| 1515 | |
| 1516 | return ret; |
| 1517 | } |
| 1518 | |
| 1519 | /* |
| 1520 | * W25Q adds an optional byte to the standard WRSR opcode. If /CS is |
| 1521 | * de-asserted after the first byte, then it acts like a JEDEC-standard |
| 1522 | * WRSR command. if /CS is asserted, then the next data byte is written |
| 1523 | * into status register 2. |
| 1524 | */ |
| 1525 | #define W25Q_WRSR_OUTSIZE 0x03 |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1526 | static int w25q_write_status_register_WREN(const struct flashctx *flash, uint8_t s1, uint8_t s2) |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1527 | { |
| 1528 | int result; |
| 1529 | struct spi_command cmds[] = { |
| 1530 | { |
| 1531 | /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ |
| 1532 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 1533 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 1534 | .readcnt = 0, |
| 1535 | .readarr = NULL, |
| 1536 | }, { |
| 1537 | .writecnt = W25Q_WRSR_OUTSIZE, |
| 1538 | .writearr = (const unsigned char[]){ JEDEC_WRSR, s1, s2 }, |
| 1539 | .readcnt = 0, |
| 1540 | .readarr = NULL, |
| 1541 | }, { |
| 1542 | .writecnt = 0, |
| 1543 | .writearr = NULL, |
| 1544 | .readcnt = 0, |
| 1545 | .readarr = NULL, |
| 1546 | }}; |
| 1547 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1548 | result = spi_send_multicommand(flash, cmds); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1549 | if (result) { |
| 1550 | msg_cerr("%s failed during command execution\n", |
| 1551 | __func__); |
| 1552 | } |
| 1553 | |
| 1554 | /* WRSR performs a self-timed erase before the changes take effect. */ |
David Hendricks | 6082404 | 2014-12-11 17:22:06 -0800 | [diff] [blame] | 1555 | programmer_delay(100 * 1000); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1556 | |
| 1557 | return result; |
| 1558 | } |
| 1559 | |
| 1560 | /* |
| 1561 | * Set/clear the SRP1 bit in status register 2. |
| 1562 | * FIXME: make this more generic if other chips use the same SR2 layout |
| 1563 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1564 | static int w25q_set_srp1(const struct flashctx *flash, int enable) |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1565 | { |
| 1566 | struct w25q_status sr1; |
| 1567 | struct w25q_status_2 sr2; |
| 1568 | uint8_t tmp, expected; |
| 1569 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1570 | tmp = do_read_status(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1571 | memcpy(&sr1, &tmp, 1); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1572 | tmp = w25q_read_status_register_2(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1573 | memcpy(&sr2, &tmp, 1); |
| 1574 | |
| 1575 | msg_cdbg("%s: old status 2: 0x%02x\n", __func__, tmp); |
| 1576 | |
| 1577 | sr2.srp1 = enable ? 1 : 0; |
| 1578 | |
| 1579 | memcpy(&expected, &sr2, 1); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1580 | w25q_write_status_register_WREN(flash, *((uint8_t *)&sr1), *((uint8_t *)&sr2)); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1581 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1582 | tmp = w25q_read_status_register_2(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1583 | msg_cdbg("%s: new status 2: 0x%02x\n", __func__, tmp); |
| 1584 | if ((tmp & MASK_WP2_AREA) != (expected & MASK_WP2_AREA)) |
| 1585 | return 1; |
| 1586 | |
| 1587 | return 0; |
| 1588 | } |
| 1589 | |
| 1590 | enum wp_mode get_wp_mode(const char *mode_str) |
| 1591 | { |
| 1592 | enum wp_mode wp_mode = WP_MODE_UNKNOWN; |
| 1593 | |
| 1594 | if (!strcasecmp(mode_str, "hardware")) |
| 1595 | wp_mode = WP_MODE_HARDWARE; |
| 1596 | else if (!strcasecmp(mode_str, "power_cycle")) |
| 1597 | wp_mode = WP_MODE_POWER_CYCLE; |
| 1598 | else if (!strcasecmp(mode_str, "permanent")) |
| 1599 | wp_mode = WP_MODE_PERMANENT; |
| 1600 | |
| 1601 | return wp_mode; |
| 1602 | } |
| 1603 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1604 | static int w25q_disable_writeprotect(const struct flashctx *flash, |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1605 | enum wp_mode wp_mode) |
| 1606 | { |
| 1607 | int ret = 1; |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1608 | struct w25q_status_2 sr2; |
| 1609 | uint8_t tmp; |
| 1610 | |
| 1611 | switch (wp_mode) { |
| 1612 | case WP_MODE_HARDWARE: |
| 1613 | ret = w25_set_srp0(flash, 0); |
| 1614 | break; |
| 1615 | case WP_MODE_POWER_CYCLE: |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1616 | tmp = w25q_read_status_register_2(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1617 | memcpy(&sr2, &tmp, 1); |
| 1618 | if (sr2.srp1) { |
| 1619 | msg_cerr("%s(): must disconnect power to disable " |
| 1620 | "write-protection\n", __func__); |
| 1621 | } else { |
| 1622 | ret = 0; |
| 1623 | } |
| 1624 | break; |
| 1625 | case WP_MODE_PERMANENT: |
| 1626 | msg_cerr("%s(): cannot disable permanent write-protection\n", |
| 1627 | __func__); |
| 1628 | break; |
| 1629 | default: |
| 1630 | msg_cerr("%s(): invalid mode specified\n", __func__); |
| 1631 | break; |
| 1632 | } |
| 1633 | |
| 1634 | if (ret) |
| 1635 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 1636 | return ret; |
| 1637 | } |
| 1638 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1639 | static int w25q_disable_writeprotect_default(const struct flashctx *flash) |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1640 | { |
| 1641 | return w25q_disable_writeprotect(flash, WP_MODE_HARDWARE); |
| 1642 | } |
| 1643 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1644 | static int w25q_enable_writeprotect(const struct flashctx *flash, |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1645 | enum wp_mode wp_mode) |
| 1646 | { |
| 1647 | int ret = 1; |
| 1648 | struct w25q_status sr1; |
| 1649 | struct w25q_status_2 sr2; |
| 1650 | uint8_t tmp; |
| 1651 | |
| 1652 | switch (wp_mode) { |
| 1653 | case WP_MODE_HARDWARE: |
| 1654 | if (w25q_disable_writeprotect(flash, WP_MODE_POWER_CYCLE)) { |
| 1655 | msg_cerr("%s(): cannot disable power cycle WP mode\n", |
| 1656 | __func__); |
| 1657 | break; |
| 1658 | } |
| 1659 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1660 | tmp = do_read_status(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1661 | memcpy(&sr1, &tmp, 1); |
| 1662 | if (sr1.srp0) |
| 1663 | ret = 0; |
| 1664 | else |
| 1665 | ret = w25_set_srp0(flash, 1); |
| 1666 | |
| 1667 | break; |
| 1668 | case WP_MODE_POWER_CYCLE: |
| 1669 | if (w25q_disable_writeprotect(flash, WP_MODE_HARDWARE)) { |
| 1670 | msg_cerr("%s(): cannot disable hardware WP mode\n", |
| 1671 | __func__); |
| 1672 | break; |
| 1673 | } |
| 1674 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1675 | tmp = w25q_read_status_register_2(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1676 | memcpy(&sr2, &tmp, 1); |
| 1677 | if (sr2.srp1) |
| 1678 | ret = 0; |
| 1679 | else |
| 1680 | ret = w25q_set_srp1(flash, 1); |
| 1681 | |
| 1682 | break; |
| 1683 | case WP_MODE_PERMANENT: |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 1684 | tmp = do_read_status(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1685 | memcpy(&sr1, &tmp, 1); |
| 1686 | if (sr1.srp0 == 0) { |
| 1687 | ret = w25_set_srp0(flash, 1); |
| 1688 | if (ret) { |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1689 | msg_perr("%s(): cannot enable SRP0 for " |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1690 | "permanent WP\n", __func__); |
| 1691 | break; |
| 1692 | } |
| 1693 | } |
| 1694 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1695 | tmp = w25q_read_status_register_2(flash); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1696 | memcpy(&sr2, &tmp, 1); |
| 1697 | if (sr2.srp1 == 0) { |
| 1698 | ret = w25q_set_srp1(flash, 1); |
| 1699 | if (ret) { |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1700 | msg_perr("%s(): cannot enable SRP1 for " |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1701 | "permanent WP\n", __func__); |
| 1702 | break; |
| 1703 | } |
| 1704 | } |
| 1705 | |
| 1706 | break; |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1707 | default: |
| 1708 | msg_perr("%s(): invalid mode %d\n", __func__, wp_mode); |
| 1709 | break; |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1710 | } |
| 1711 | |
| 1712 | if (ret) |
| 1713 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 1714 | return ret; |
| 1715 | } |
| 1716 | |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1717 | /* FIXME: Move to spi25.c if it's a JEDEC standard opcode */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1718 | uint8_t mx25l_read_config_register(const struct flashctx *flash) |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1719 | { |
| 1720 | static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x15 }; |
| 1721 | unsigned char readarr[2]; /* leave room for dummy byte */ |
| 1722 | int ret; |
| 1723 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 1724 | ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1725 | if (ret) { |
Duncan Laurie | 870d8af | 2019-01-09 18:05:23 -0800 | [diff] [blame] | 1726 | msg_cdbg("RDCR failed!\n"); |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1727 | readarr[0] = 0x00; |
| 1728 | } |
| 1729 | |
| 1730 | return readarr[0]; |
| 1731 | } |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1732 | /* W25P, W25X, and many flash chips from various vendors */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1733 | struct wp wp_w25 = { |
David Hendricks | 0f7f538 | 2011-02-11 18:12:31 -0800 | [diff] [blame] | 1734 | .list_ranges = w25_list_ranges, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1735 | .set_range = w25_set_range, |
| 1736 | .enable = w25_enable_writeprotect, |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1737 | .disable = w25_disable_writeprotect, |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1738 | .wp_status = w25_wp_status, |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1739 | |
| 1740 | }; |
| 1741 | |
| 1742 | /* W25Q series has features such as a second status register and SFDP */ |
| 1743 | struct wp wp_w25q = { |
| 1744 | .list_ranges = w25_list_ranges, |
| 1745 | .set_range = w25_set_range, |
| 1746 | .enable = w25q_enable_writeprotect, |
| 1747 | /* |
| 1748 | * By default, disable hardware write-protection. We may change |
| 1749 | * this later if we want to add fine-grained write-protect disable |
| 1750 | * as a command-line option. |
| 1751 | */ |
| 1752 | .disable = w25q_disable_writeprotect_default, |
| 1753 | .wp_status = w25q_wp_status, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1754 | }; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1755 | |
Duncan Laurie | 1801f7c | 2019-01-09 18:02:51 -0800 | [diff] [blame] | 1756 | /* W25Q large series has 4 block-protect bits */ |
| 1757 | struct wp wp_w25q_large = { |
| 1758 | .list_ranges = w25_list_ranges, |
| 1759 | .set_range = w25q_large_set_range, |
| 1760 | .enable = w25q_enable_writeprotect, |
| 1761 | /* |
| 1762 | * By default, disable hardware write-protection. We may change |
| 1763 | * this later if we want to add fine-grained write-protect disable |
| 1764 | * as a command-line option. |
| 1765 | */ |
| 1766 | .disable = w25q_disable_writeprotect_default, |
| 1767 | .wp_status = w25q_large_wp_status, |
| 1768 | }; |
| 1769 | |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1770 | struct generic_range gd25q32_cmp0_ranges[] = { |
| 1771 | /* none, bp4 and bp3 => don't care */ |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1772 | { { }, 0x00, {0, 0} }, |
| 1773 | { { }, 0x08, {0, 0} }, |
| 1774 | { { }, 0x10, {0, 0} }, |
| 1775 | { { }, 0x18, {0, 0} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1776 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1777 | { { }, 0x01, {0x3f0000, 64 * 1024} }, |
| 1778 | { { }, 0x02, {0x3e0000, 128 * 1024} }, |
| 1779 | { { }, 0x03, {0x3c0000, 256 * 1024} }, |
| 1780 | { { }, 0x04, {0x380000, 512 * 1024} }, |
| 1781 | { { }, 0x05, {0x300000, 1024 * 1024} }, |
| 1782 | { { }, 0x06, {0x200000, 2048 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1783 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1784 | { { }, 0x09, {0x000000, 64 * 1024} }, |
| 1785 | { { }, 0x0a, {0x000000, 128 * 1024} }, |
| 1786 | { { }, 0x0b, {0x000000, 256 * 1024} }, |
| 1787 | { { }, 0x0c, {0x000000, 512 * 1024} }, |
| 1788 | { { }, 0x0d, {0x000000, 1024 * 1024} }, |
| 1789 | { { }, 0x0e, {0x000000, 2048 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1790 | |
| 1791 | /* all, bp4 and bp3 => don't care */ |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1792 | { { }, 0x07, {0x000000, 4096 * 1024} }, |
| 1793 | { { }, 0x0f, {0x000000, 4096 * 1024} }, |
| 1794 | { { }, 0x17, {0x000000, 4096 * 1024} }, |
| 1795 | { { }, 0x1f, {0x000000, 4096 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1796 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1797 | { { }, 0x11, {0x3ff000, 4 * 1024} }, |
| 1798 | { { }, 0x12, {0x3fe000, 8 * 1024} }, |
| 1799 | { { }, 0x13, {0x3fc000, 16 * 1024} }, |
| 1800 | { { }, 0x14, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */ |
| 1801 | { { }, 0x15, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */ |
| 1802 | { { }, 0x16, {0x3f8000, 32 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1803 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1804 | { { }, 0x19, {0x000000, 4 * 1024} }, |
| 1805 | { { }, 0x1a, {0x000000, 8 * 1024} }, |
| 1806 | { { }, 0x1b, {0x000000, 16 * 1024} }, |
| 1807 | { { }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */ |
| 1808 | { { }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */ |
| 1809 | { { }, 0x1e, {0x000000, 32 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1810 | }; |
| 1811 | |
| 1812 | struct generic_range gd25q32_cmp1_ranges[] = { |
Martin Roth | 563a1fe | 2017-04-18 14:26:27 -0600 | [diff] [blame] | 1813 | /* All, bp4 and bp3 => don't care */ |
| 1814 | { { }, 0x00, {0x000000, 4096 * 1024} }, /* All */ |
| 1815 | { { }, 0x08, {0x000000, 4096 * 1024} }, |
| 1816 | { { }, 0x10, {0x000000, 4096 * 1024} }, |
| 1817 | { { }, 0x18, {0x000000, 4096 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1818 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1819 | { { }, 0x01, {0x000000, 4032 * 1024} }, |
| 1820 | { { }, 0x02, {0x000000, 3968 * 1024} }, |
| 1821 | { { }, 0x03, {0x000000, 3840 * 1024} }, |
| 1822 | { { }, 0x04, {0x000000, 3584 * 1024} }, |
| 1823 | { { }, 0x05, {0x000000, 3 * 1024 * 1024} }, |
| 1824 | { { }, 0x06, {0x000000, 2 * 1024 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1825 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1826 | { { }, 0x09, {0x010000, 4032 * 1024} }, |
| 1827 | { { }, 0x0a, {0x020000, 3968 * 1024} }, |
| 1828 | { { }, 0x0b, {0x040000, 3840 * 1024} }, |
| 1829 | { { }, 0x0c, {0x080000, 3584 * 1024} }, |
| 1830 | { { }, 0x0d, {0x100000, 3 * 1024 * 1024} }, |
| 1831 | { { }, 0x0e, {0x200000, 2 * 1024 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1832 | |
Martin Roth | 563a1fe | 2017-04-18 14:26:27 -0600 | [diff] [blame] | 1833 | /* None, bp4 and bp3 => don't care */ |
| 1834 | { { }, 0x07, {0, 0} }, /* None */ |
| 1835 | { { }, 0x0f, {0, 0} }, |
| 1836 | { { }, 0x17, {0, 0} }, |
| 1837 | { { }, 0x1f, {0, 0} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1838 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1839 | { { }, 0x11, {0x000000, 4092 * 1024} }, |
| 1840 | { { }, 0x12, {0x000000, 4088 * 1024} }, |
| 1841 | { { }, 0x13, {0x000000, 4080 * 1024} }, |
| 1842 | { { }, 0x14, {0x000000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1843 | { { }, 0x15, {0x000000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1844 | { { }, 0x16, {0x000000, 4064 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1845 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1846 | { { }, 0x19, {0x001000, 4092 * 1024} }, |
| 1847 | { { }, 0x1a, {0x002000, 4088 * 1024} }, |
| 1848 | { { }, 0x1b, {0x040000, 4080 * 1024} }, |
| 1849 | { { }, 0x1c, {0x080000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1850 | { { }, 0x1d, {0x080000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1851 | { { }, 0x1e, {0x080000, 4064 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1852 | }; |
| 1853 | |
| 1854 | static struct generic_wp gd25q32_wp = { |
| 1855 | /* TODO: map second status register */ |
| 1856 | .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 }, |
| 1857 | }; |
| 1858 | |
David Hendricks | 1e9d7ca | 2016-03-14 15:50:34 -0700 | [diff] [blame] | 1859 | struct generic_range gd25q128_cmp0_ranges[] = { |
| 1860 | /* none, bp4 and bp3 => don't care, others = 0 */ |
| 1861 | { { .tb = 0 }, 0x00, {0, 0} }, |
| 1862 | { { .tb = 0 }, 0x08, {0, 0} }, |
| 1863 | { { .tb = 0 }, 0x10, {0, 0} }, |
| 1864 | { { .tb = 0 }, 0x18, {0, 0} }, |
| 1865 | |
| 1866 | { { .tb = 0 }, 0x01, {0xfc0000, 256 * 1024} }, |
| 1867 | { { .tb = 0 }, 0x02, {0xf80000, 512 * 1024} }, |
| 1868 | { { .tb = 0 }, 0x03, {0xf00000, 1024 * 1024} }, |
| 1869 | { { .tb = 0 }, 0x04, {0xe00000, 2048 * 1024} }, |
| 1870 | { { .tb = 0 }, 0x05, {0xc00000, 4096 * 1024} }, |
| 1871 | { { .tb = 0 }, 0x06, {0x800000, 8192 * 1024} }, |
| 1872 | |
| 1873 | { { .tb = 0 }, 0x09, {0x000000, 256 * 1024} }, |
| 1874 | { { .tb = 0 }, 0x0a, {0x000000, 512 * 1024} }, |
| 1875 | { { .tb = 0 }, 0x0b, {0x000000, 1024 * 1024} }, |
| 1876 | { { .tb = 0 }, 0x0c, {0x000000, 2048 * 1024} }, |
| 1877 | { { .tb = 0 }, 0x0d, {0x000000, 4096 * 1024} }, |
| 1878 | { { .tb = 0 }, 0x0e, {0x000000, 8192 * 1024} }, |
| 1879 | |
| 1880 | /* all, bp4 and bp3 => don't care, others = 1 */ |
| 1881 | { { .tb = 0 }, 0x07, {0x000000, 16384 * 1024} }, |
| 1882 | { { .tb = 0 }, 0x0f, {0x000000, 16384 * 1024} }, |
| 1883 | { { .tb = 0 }, 0x17, {0x000000, 16384 * 1024} }, |
| 1884 | { { .tb = 0 }, 0x1f, {0x000000, 16384 * 1024} }, |
| 1885 | |
| 1886 | { { .tb = 0 }, 0x11, {0xfff000, 4 * 1024} }, |
| 1887 | { { .tb = 0 }, 0x12, {0xffe000, 8 * 1024} }, |
| 1888 | { { .tb = 0 }, 0x13, {0xffc000, 16 * 1024} }, |
| 1889 | { { .tb = 0 }, 0x14, {0xff8000, 32 * 1024} }, /* bp0 => don't care */ |
| 1890 | { { .tb = 0 }, 0x15, {0xff8000, 32 * 1024} }, /* bp0 => don't care */ |
| 1891 | |
| 1892 | { { .tb = 0 }, 0x19, {0x000000, 4 * 1024} }, |
| 1893 | { { .tb = 0 }, 0x1a, {0x000000, 8 * 1024} }, |
| 1894 | { { .tb = 0 }, 0x1b, {0x000000, 16 * 1024} }, |
| 1895 | { { .tb = 0 }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */ |
| 1896 | { { .tb = 0 }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */ |
| 1897 | { { .tb = 0 }, 0x1e, {0x000000, 32 * 1024} }, |
| 1898 | }; |
| 1899 | |
| 1900 | struct generic_range gd25q128_cmp1_ranges[] = { |
| 1901 | /* none, bp4 and bp3 => don't care, others = 0 */ |
| 1902 | { { .tb = 1 }, 0x00, {0x000000, 16384 * 1024} }, |
| 1903 | { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} }, |
| 1904 | { { .tb = 1 }, 0x10, {0x000000, 16384 * 1024} }, |
| 1905 | { { .tb = 1 }, 0x18, {0x000000, 16384 * 1024} }, |
| 1906 | |
| 1907 | { { .tb = 1 }, 0x01, {0x000000, 16128 * 1024} }, |
| 1908 | { { .tb = 1 }, 0x02, {0x000000, 15872 * 1024} }, |
| 1909 | { { .tb = 1 }, 0x03, {0x000000, 15360 * 1024} }, |
| 1910 | { { .tb = 1 }, 0x04, {0x000000, 14336 * 1024} }, |
| 1911 | { { .tb = 1 }, 0x05, {0x000000, 12288 * 1024} }, |
| 1912 | { { .tb = 1 }, 0x06, {0x000000, 8192 * 1024} }, |
| 1913 | |
| 1914 | { { .tb = 1 }, 0x09, {0x000000, 16128 * 1024} }, |
| 1915 | { { .tb = 1 }, 0x0a, {0x000000, 15872 * 1024} }, |
| 1916 | { { .tb = 1 }, 0x0b, {0x000000, 15360 * 1024} }, |
| 1917 | { { .tb = 1 }, 0x0c, {0x000000, 14336 * 1024} }, |
| 1918 | { { .tb = 1 }, 0x0d, {0x000000, 12288 * 1024} }, |
| 1919 | { { .tb = 1 }, 0x0e, {0x000000, 8192 * 1024} }, |
| 1920 | |
| 1921 | /* none, bp4 and bp3 => don't care, others = 1 */ |
| 1922 | { { .tb = 1 }, 0x07, {0x000000, 16384 * 1024} }, |
| 1923 | { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} }, |
| 1924 | { { .tb = 1 }, 0x0f, {0x000000, 16384 * 1024} }, |
| 1925 | { { .tb = 1 }, 0x17, {0x000000, 16384 * 1024} }, |
| 1926 | { { .tb = 1 }, 0x1f, {0x000000, 16384 * 1024} }, |
| 1927 | |
| 1928 | { { .tb = 1 }, 0x11, {0x000000, 16380 * 1024} }, |
| 1929 | { { .tb = 1 }, 0x12, {0x000000, 16376 * 1024} }, |
| 1930 | { { .tb = 1 }, 0x13, {0x000000, 16368 * 1024} }, |
| 1931 | { { .tb = 1 }, 0x14, {0x000000, 16352 * 1024} }, /* bp0 => don't care */ |
| 1932 | { { .tb = 1 }, 0x15, {0x000000, 16352 * 1024} }, /* bp0 => don't care */ |
| 1933 | |
| 1934 | { { .tb = 1 }, 0x19, {0x001000, 16380 * 1024} }, |
| 1935 | { { .tb = 1 }, 0x1a, {0x002000, 16376 * 1024} }, |
| 1936 | { { .tb = 1 }, 0x1b, {0x004000, 16368 * 1024} }, |
| 1937 | { { .tb = 1 }, 0x1c, {0x008000, 16352 * 1024} }, /* bp0 => don't care */ |
| 1938 | { { .tb = 1 }, 0x1d, {0x008000, 16352 * 1024} }, /* bp0 => don't care */ |
| 1939 | { { .tb = 1 }, 0x1e, {0x008000, 16352 * 1024} }, |
| 1940 | }; |
| 1941 | |
| 1942 | static struct generic_wp gd25q128_wp = { |
| 1943 | /* TODO: map second and third status registers */ |
| 1944 | .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 }, |
| 1945 | }; |
| 1946 | |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1947 | #if 0 |
| 1948 | /* FIXME: MX25L6405D has same ID as MX25L6406 */ |
| 1949 | static struct w25q_range mx25l6405d_ranges[] = { |
| 1950 | { X, 0, 0, {0, 0} }, /* none */ |
| 1951 | { X, 0, 0x1, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */ |
| 1952 | { X, 0, 0x2, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */ |
| 1953 | { X, 0, 0x3, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */ |
| 1954 | { X, 0, 0x4, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */ |
| 1955 | { X, 0, 0x5, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */ |
| 1956 | { X, 0, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 1957 | { X, 0, 0x7, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */ |
| 1958 | |
| 1959 | { X, 1, 0x0, {0x000000, 8192 * 1024} }, |
| 1960 | { X, 1, 0x1, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 1961 | { X, 1, 0x2, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */ |
| 1962 | { X, 1, 0x3, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */ |
| 1963 | { X, 1, 0x4, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */ |
| 1964 | { X, 1, 0x5, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */ |
| 1965 | { X, 1, 0x6, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */ |
| 1966 | { X, 1, 0x7, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */ |
| 1967 | }; |
| 1968 | #endif |
| 1969 | |
| 1970 | /* FIXME: MX25L6406 has same ID as MX25L6405D */ |
| 1971 | struct generic_range mx25l6406e_ranges[] = { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1972 | { { }, 0, {0, 0} }, /* none */ |
| 1973 | { { }, 0x1, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */ |
| 1974 | { { }, 0x2, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */ |
| 1975 | { { }, 0x3, {0x7a0000, 64 * 8 * 1024} }, /* blocks 120-127 */ |
| 1976 | { { }, 0x4, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */ |
| 1977 | { { }, 0x5, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */ |
| 1978 | { { }, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1979 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1980 | { { }, 0x7, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1981 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1982 | { { }, 0x9, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 1983 | { { }, 0xa, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */ |
| 1984 | { { }, 0xb, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */ |
| 1985 | { { }, 0xc, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */ |
| 1986 | { { }, 0xd, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */ |
| 1987 | { { }, 0xe, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */ |
| 1988 | { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */ |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1989 | }; |
| 1990 | |
| 1991 | static struct generic_wp mx25l6406e_wp = { |
| 1992 | .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 }, |
| 1993 | .ranges = &mx25l6406e_ranges[0], |
| 1994 | }; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1995 | |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1996 | struct generic_range mx25l6495f_tb0_ranges[] = { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1997 | { { }, 0, {0, 0} }, /* none */ |
| 1998 | { { }, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */ |
| 1999 | { { }, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */ |
| 2000 | { { }, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */ |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 2001 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2002 | { { }, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */ |
| 2003 | { { }, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */ |
| 2004 | { { }, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */ |
| 2005 | { { }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 2006 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2007 | { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2008 | { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2009 | { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2010 | { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2011 | { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2012 | { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2013 | { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */ |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 2014 | }; |
| 2015 | |
| 2016 | struct generic_range mx25l6495f_tb1_ranges[] = { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2017 | { { }, 0, {0, 0} }, /* none */ |
| 2018 | { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */ |
| 2019 | { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */ |
| 2020 | { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */ |
| 2021 | { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */ |
| 2022 | { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */ |
| 2023 | { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 2024 | { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 2025 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2026 | { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2027 | { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2028 | { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2029 | { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2030 | { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2031 | { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 2032 | { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */ |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 2033 | }; |
| 2034 | |
| 2035 | static struct generic_wp mx25l6495f_wp = { |
| 2036 | .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 }, |
| 2037 | }; |
| 2038 | |
Vic Yang | 848bfd1 | 2018-03-23 10:24:07 -0700 | [diff] [blame] | 2039 | struct generic_range mx25l25635f_tb0_ranges[] = { |
| 2040 | { { }, 0, {0, 0} }, /* none */ |
| 2041 | { { }, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* block 511 */ |
| 2042 | { { }, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* blocks 510-511 */ |
| 2043 | { { }, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* blocks 508-511 */ |
| 2044 | { { }, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* blocks 504-511 */ |
| 2045 | { { }, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* blocks 496-511 */ |
| 2046 | { { }, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* blocks 480-511 */ |
| 2047 | { { }, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* blocks 448-511 */ |
| 2048 | { { }, 0x8, {0x1800000, 64 * 128 * 1024} }, /* blocks 384-511 */ |
| 2049 | { { }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* blocks 256-511 */ |
| 2050 | { { }, 0xa, {0x0000000, 64 * 512 * 1024} }, /* all */ |
| 2051 | { { }, 0xb, {0x0000000, 64 * 512 * 1024} }, /* all */ |
| 2052 | { { }, 0xc, {0x0000000, 64 * 512 * 1024} }, /* all */ |
| 2053 | { { }, 0xd, {0x0000000, 64 * 512 * 1024} }, /* all */ |
| 2054 | { { }, 0xe, {0x0000000, 64 * 512 * 1024} }, /* all */ |
| 2055 | { { }, 0xf, {0x0000000, 64 * 512 * 1024} }, /* all */ |
| 2056 | }; |
| 2057 | |
| 2058 | struct generic_range mx25l25635f_tb1_ranges[] = { |
| 2059 | { { }, 0, {0, 0} }, /* none */ |
| 2060 | { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */ |
| 2061 | { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */ |
| 2062 | { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */ |
| 2063 | { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */ |
| 2064 | { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */ |
| 2065 | { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 2066 | { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 2067 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */ |
| 2068 | { { }, 0x9, {0x000000, 64 * 256 * 1024} }, /* blocks 0-255 */ |
| 2069 | { { }, 0xa, {0x000000, 64 * 512 * 1024} }, /* all */ |
| 2070 | { { }, 0xb, {0x000000, 64 * 512 * 1024} }, /* all */ |
| 2071 | { { }, 0xc, {0x000000, 64 * 512 * 1024} }, /* all */ |
| 2072 | { { }, 0xd, {0x000000, 64 * 512 * 1024} }, /* all */ |
| 2073 | { { }, 0xe, {0x000000, 64 * 512 * 1024} }, /* all */ |
| 2074 | { { }, 0xf, {0x000000, 64 * 512 * 1024} }, /* all */ |
| 2075 | }; |
| 2076 | |
| 2077 | static struct generic_wp mx25l25635f_wp = { |
| 2078 | .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 }, |
| 2079 | }; |
| 2080 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2081 | struct generic_range s25fs128s_ranges[] = { |
| 2082 | { { .tb = 1 }, 0, {0, 0} }, /* none */ |
| 2083 | { { .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* lower 64th */ |
| 2084 | { { .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* lower 32nd */ |
| 2085 | { { .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* lower 16th */ |
| 2086 | { { .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* lower 8th */ |
| 2087 | { { .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* lower 4th */ |
| 2088 | { { .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* lower half */ |
| 2089 | { { .tb = 1 }, 0x7, {0x000000, 16384 * 1024} }, /* all */ |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2090 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2091 | { { .tb = 0 }, 0, {0, 0} }, /* none */ |
| 2092 | { { .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* upper 64th */ |
| 2093 | { { .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* upper 32nd */ |
| 2094 | { { .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* upper 16th */ |
| 2095 | { { .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* upper 8th */ |
| 2096 | { { .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* upper 4th */ |
| 2097 | { { .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* upper half */ |
| 2098 | { { .tb = 0 }, 0x7, {0x000000, 16384 * 1024} }, /* all */ |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2099 | }; |
| 2100 | |
| 2101 | static struct generic_wp s25fs128s_wp = { |
| 2102 | .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 }, |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2103 | .get_modifier_bits = s25f_get_modifier_bits, |
| 2104 | .set_modifier_bits = s25f_set_modifier_bits, |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2105 | }; |
| 2106 | |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 2107 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2108 | struct generic_range s25fl256s_ranges[] = { |
| 2109 | { { .tb = 1 }, 0, {0, 0} }, /* none */ |
| 2110 | { { .tb = 1 }, 0x1, {0x000000, 512 * 1024} }, /* lower 64th */ |
| 2111 | { { .tb = 1 }, 0x2, {0x000000, 1024 * 1024} }, /* lower 32nd */ |
| 2112 | { { .tb = 1 }, 0x3, {0x000000, 2048 * 1024} }, /* lower 16th */ |
| 2113 | { { .tb = 1 }, 0x4, {0x000000, 4096 * 1024} }, /* lower 8th */ |
| 2114 | { { .tb = 1 }, 0x5, {0x000000, 8192 * 1024} }, /* lower 4th */ |
| 2115 | { { .tb = 1 }, 0x6, {0x000000, 16384 * 1024} }, /* lower half */ |
| 2116 | { { .tb = 1 }, 0x7, {0x000000, 32768 * 1024} }, /* all */ |
| 2117 | |
| 2118 | { { .tb = 0 }, 0, {0, 0} }, /* none */ |
| 2119 | { { .tb = 0 }, 0x1, {0x1f80000, 512 * 1024} }, /* upper 64th */ |
| 2120 | { { .tb = 0 }, 0x2, {0x1f00000, 1024 * 1024} }, /* upper 32nd */ |
| 2121 | { { .tb = 0 }, 0x3, {0x1e00000, 2048 * 1024} }, /* upper 16th */ |
| 2122 | { { .tb = 0 }, 0x4, {0x1c00000, 4096 * 1024} }, /* upper 8th */ |
| 2123 | { { .tb = 0 }, 0x5, {0x1800000, 8192 * 1024} }, /* upper 4th */ |
| 2124 | { { .tb = 0 }, 0x6, {0x1000000, 16384 * 1024} }, /* upper half */ |
| 2125 | { { .tb = 0 }, 0x7, {0x000000, 32768 * 1024} }, /* all */ |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 2126 | }; |
| 2127 | |
| 2128 | static struct generic_wp s25fl256s_wp = { |
| 2129 | .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 }, |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2130 | .get_modifier_bits = s25f_get_modifier_bits, |
| 2131 | .set_modifier_bits = s25f_set_modifier_bits, |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 2132 | }; |
| 2133 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2134 | /* Given a flash chip, this function returns its writeprotect info. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2135 | static int generic_range_table(const struct flashctx *flash, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2136 | struct generic_wp **wp, |
| 2137 | int *num_entries) |
| 2138 | { |
| 2139 | *wp = NULL; |
| 2140 | *num_entries = 0; |
| 2141 | |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2142 | switch (flash->chip->manufacture_id) { |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 2143 | case GIGADEVICE_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2144 | switch(flash->chip->model_id) { |
David Hendricks | 1e9d7ca | 2016-03-14 15:50:34 -0700 | [diff] [blame] | 2145 | |
Martin Roth | 563a1fe | 2017-04-18 14:26:27 -0600 | [diff] [blame] | 2146 | case GIGADEVICE_GD25LQ32: |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 2147 | case GIGADEVICE_GD25Q32: { |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2148 | uint8_t sr1 = w25q_read_status_register_2(flash); |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 2149 | *wp = &gd25q32_wp; |
David Hendricks | 1e9d7ca | 2016-03-14 15:50:34 -0700 | [diff] [blame] | 2150 | |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 2151 | if (!(sr1 & (1 << 6))) { /* CMP == 0 */ |
| 2152 | (*wp)->ranges = &gd25q32_cmp0_ranges[0]; |
| 2153 | *num_entries = ARRAY_SIZE(gd25q32_cmp0_ranges); |
| 2154 | } else { /* CMP == 1 */ |
| 2155 | (*wp)->ranges = &gd25q32_cmp1_ranges[0]; |
| 2156 | *num_entries = ARRAY_SIZE(gd25q32_cmp1_ranges); |
| 2157 | } |
| 2158 | |
| 2159 | break; |
David Hendricks | 1e9d7ca | 2016-03-14 15:50:34 -0700 | [diff] [blame] | 2160 | } |
Furquan Shaikh | 62cd810 | 2016-07-17 23:04:06 -0700 | [diff] [blame] | 2161 | case GIGADEVICE_GD25Q128: |
Aaron Durbin | 6c957d7 | 2018-08-20 09:31:01 -0600 | [diff] [blame] | 2162 | case GIGADEVICE_GD25LQ128CD: { |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2163 | uint8_t sr1 = w25q_read_status_register_2(flash); |
David Hendricks | 1e9d7ca | 2016-03-14 15:50:34 -0700 | [diff] [blame] | 2164 | *wp = &gd25q128_wp; |
| 2165 | |
| 2166 | if (!(sr1 & (1 << 6))) { /* CMP == 0 */ |
| 2167 | (*wp)->ranges = &gd25q128_cmp0_ranges[0]; |
| 2168 | *num_entries = ARRAY_SIZE(gd25q128_cmp0_ranges); |
| 2169 | } else { /* CMP == 1 */ |
| 2170 | (*wp)->ranges = &gd25q128_cmp1_ranges[0]; |
| 2171 | *num_entries = ARRAY_SIZE(gd25q128_cmp1_ranges); |
| 2172 | } |
| 2173 | |
| 2174 | break; |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 2175 | } |
| 2176 | default: |
| 2177 | msg_cerr("%s() %d: GigaDevice flash chip mismatch" |
| 2178 | " (0x%04x), aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2179 | flash->chip->model_id); |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 2180 | return -1; |
| 2181 | } |
| 2182 | break; |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 2183 | case MACRONIX_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2184 | switch (flash->chip->model_id) { |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 2185 | case MACRONIX_MX25L6405: |
| 2186 | /* FIXME: MX25L64* chips have mixed capabilities and |
| 2187 | share IDs */ |
| 2188 | *wp = &mx25l6406e_wp; |
| 2189 | *num_entries = ARRAY_SIZE(mx25l6406e_ranges); |
| 2190 | break; |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 2191 | case MACRONIX_MX25L6495F: { |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2192 | uint8_t cr = mx25l_read_config_register(flash); |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 2193 | |
| 2194 | *wp = &mx25l6495f_wp; |
| 2195 | if (!(cr & (1 << 3))) { /* T/B == 0 */ |
| 2196 | (*wp)->ranges = &mx25l6495f_tb0_ranges[0]; |
| 2197 | *num_entries = ARRAY_SIZE(mx25l6495f_tb0_ranges); |
| 2198 | } else { /* T/B == 1 */ |
| 2199 | (*wp)->ranges = &mx25l6495f_tb1_ranges[0]; |
| 2200 | *num_entries = ARRAY_SIZE(mx25l6495f_tb1_ranges); |
| 2201 | } |
| 2202 | break; |
| 2203 | } |
Vic Yang | 848bfd1 | 2018-03-23 10:24:07 -0700 | [diff] [blame] | 2204 | case MACRONIX_MX25L25635F: { |
| 2205 | uint8_t cr = mx25l_read_config_register(flash); |
| 2206 | |
| 2207 | *wp = &mx25l25635f_wp; |
| 2208 | if (!(cr & (1 << 3))) { /* T/B == 0 */ |
| 2209 | (*wp)->ranges = &mx25l25635f_tb0_ranges[0]; |
| 2210 | *num_entries = ARRAY_SIZE(mx25l25635f_tb0_ranges); |
| 2211 | } else { /* T/B == 1 */ |
| 2212 | (*wp)->ranges = &mx25l25635f_tb1_ranges[0]; |
| 2213 | *num_entries = ARRAY_SIZE(mx25l25635f_tb1_ranges); |
| 2214 | } |
| 2215 | break; |
| 2216 | } |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 2217 | default: |
| 2218 | msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)" |
| 2219 | ", aborting\n", __func__, __LINE__, |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2220 | flash->chip->model_id); |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 2221 | return -1; |
| 2222 | } |
| 2223 | break; |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2224 | case SPANSION_ID: |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2225 | switch (flash->chip->model_id) { |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2226 | case SPANSION_S25FS128S_L: |
| 2227 | case SPANSION_S25FS128S_S: { |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2228 | *wp = &s25fs128s_wp; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2229 | (*wp)->ranges = s25fs128s_ranges; |
| 2230 | *num_entries = ARRAY_SIZE(s25fs128s_ranges); |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2231 | break; |
| 2232 | } |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 2233 | case SPANSION_S25FL256S_UL: |
| 2234 | case SPANSION_S25FL256S_US: { |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 2235 | *wp = &s25fl256s_wp; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2236 | (*wp)->ranges = s25fl256s_ranges; |
| 2237 | *num_entries = ARRAY_SIZE(s25fl256s_ranges); |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 2238 | break; |
| 2239 | } |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2240 | default: |
| 2241 | msg_cerr("%s():%d Spansion flash chip mismatch (0x%04x)" |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2242 | ", aborting\n", __func__, __LINE__, |
| 2243 | flash->chip->model_id); |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 2244 | return -1; |
| 2245 | } |
| 2246 | break; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2247 | default: |
| 2248 | msg_cerr("%s: flash vendor (0x%x) not found, aborting\n", |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 2249 | __func__, flash->chip->manufacture_id); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2250 | return -1; |
| 2251 | } |
| 2252 | |
| 2253 | return 0; |
| 2254 | } |
| 2255 | |
| 2256 | /* Given a [start, len], this function finds a block protect bit combination |
| 2257 | * (if possible) and sets the corresponding bits in "status". Remaining bits |
| 2258 | * are preserved. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2259 | static int generic_range_to_status(const struct flashctx *flash, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2260 | unsigned int start, unsigned int len, |
| 2261 | uint8_t *status) |
| 2262 | { |
| 2263 | struct generic_wp *wp; |
| 2264 | struct generic_range *r; |
| 2265 | int i, range_found = 0, num_entries; |
| 2266 | uint8_t bp_mask; |
| 2267 | |
| 2268 | if (generic_range_table(flash, &wp, &num_entries)) |
| 2269 | return -1; |
| 2270 | |
| 2271 | bp_mask = ((1 << (wp->sr1.bp0_pos + wp->sr1.bp_bits)) - 1) - \ |
| 2272 | ((1 << wp->sr1.bp0_pos) - 1); |
| 2273 | |
| 2274 | for (i = 0, r = &wp->ranges[0]; i < num_entries; i++, r++) { |
| 2275 | msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n", |
| 2276 | start, len, r->range.start, r->range.len); |
| 2277 | if ((start == r->range.start) && (len == r->range.len)) { |
| 2278 | *status &= ~(bp_mask); |
| 2279 | *status |= r->bp << (wp->sr1.bp0_pos); |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2280 | |
| 2281 | if (wp->set_modifier_bits) { |
| 2282 | if (wp->set_modifier_bits(flash, &r->m) < 0) { |
| 2283 | msg_cerr("error setting modifier " |
| 2284 | "bits for range.\n"); |
| 2285 | return -1; |
| 2286 | } |
| 2287 | } |
| 2288 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2289 | range_found = 1; |
| 2290 | break; |
| 2291 | } |
| 2292 | } |
| 2293 | |
| 2294 | if (!range_found) { |
| 2295 | msg_cerr("matching range not found\n"); |
| 2296 | return -1; |
| 2297 | } |
| 2298 | return 0; |
| 2299 | } |
| 2300 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2301 | static int generic_status_to_range(const struct flashctx *flash, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2302 | const uint8_t sr1, unsigned int *start, unsigned int *len) |
| 2303 | { |
| 2304 | struct generic_wp *wp; |
| 2305 | struct generic_range *r; |
Duncan Laurie | 04ca117 | 2015-03-12 09:25:34 -0700 | [diff] [blame] | 2306 | int num_entries, i, status_found = 0; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2307 | uint8_t sr1_bp; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2308 | struct generic_modifier_bits m; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2309 | |
| 2310 | if (generic_range_table(flash, &wp, &num_entries)) |
| 2311 | return -1; |
| 2312 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2313 | /* modifier bits may be compared more than once, so get them here */ |
| 2314 | if (wp->get_modifier_bits) { |
| 2315 | if (wp->get_modifier_bits(flash, &m) < 0) |
| 2316 | return -1; |
| 2317 | } |
| 2318 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2319 | sr1_bp = (sr1 >> wp->sr1.bp0_pos) & ((1 << wp->sr1.bp_bits) - 1); |
| 2320 | |
| 2321 | for (i = 0, r = &wp->ranges[0]; i < num_entries; i++, r++) { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 2322 | if (wp->get_modifier_bits) { |
| 2323 | if (memcmp(&m, &r->m, sizeof(m))) |
| 2324 | continue; |
| 2325 | } |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2326 | msg_cspew("comparing 0x%02x 0x%02x\n", sr1_bp, r->bp); |
| 2327 | if (sr1_bp == r->bp) { |
| 2328 | *start = r->range.start; |
| 2329 | *len = r->range.len; |
| 2330 | status_found = 1; |
| 2331 | break; |
| 2332 | } |
| 2333 | } |
| 2334 | |
| 2335 | if (!status_found) { |
| 2336 | msg_cerr("matching status not found\n"); |
| 2337 | return -1; |
| 2338 | } |
| 2339 | return 0; |
| 2340 | } |
| 2341 | |
| 2342 | /* Given a [start, len], this function calls generic_range_to_status() to |
| 2343 | * convert it to flash-chip-specific range bits, then sets into status register. |
| 2344 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2345 | static int generic_set_range(const struct flashctx *flash, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2346 | unsigned int start, unsigned int len) |
| 2347 | { |
| 2348 | uint8_t status, expected; |
| 2349 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2350 | status = do_read_status(flash); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2351 | msg_cdbg("%s: old status: 0x%02x\n", __func__, status); |
| 2352 | |
| 2353 | expected = status; /* preserve non-bp bits */ |
| 2354 | if (generic_range_to_status(flash, start, len, &expected)) |
| 2355 | return -1; |
| 2356 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2357 | do_write_status(flash, expected); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2358 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2359 | status = do_read_status(flash); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2360 | msg_cdbg("%s: new status: 0x%02x\n", __func__, status); |
| 2361 | if (status != expected) { |
| 2362 | msg_cerr("expected=0x%02x, but actual=0x%02x.\n", |
| 2363 | expected, status); |
| 2364 | return 1; |
| 2365 | } |
| 2366 | |
| 2367 | return 0; |
| 2368 | } |
| 2369 | |
| 2370 | /* Set/clear the status regsiter write protect bit in SR1. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2371 | static int generic_set_srp0(const struct flashctx *flash, int enable) |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2372 | { |
| 2373 | uint8_t status, expected; |
| 2374 | struct generic_wp *wp; |
| 2375 | int num_entries; |
| 2376 | |
| 2377 | if (generic_range_table(flash, &wp, &num_entries)) |
| 2378 | return -1; |
| 2379 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2380 | expected = do_read_status(flash); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2381 | msg_cdbg("%s: old status: 0x%02x\n", __func__, expected); |
| 2382 | |
| 2383 | if (enable) |
| 2384 | expected |= 1 << wp->sr1.srp_pos; |
| 2385 | else |
| 2386 | expected &= ~(1 << wp->sr1.srp_pos); |
| 2387 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2388 | do_write_status(flash, expected); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2389 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2390 | status = do_read_status(flash); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2391 | msg_cdbg("%s: new status: 0x%02x\n", __func__, status); |
| 2392 | if (status != expected) |
| 2393 | return -1; |
| 2394 | |
| 2395 | return 0; |
| 2396 | } |
| 2397 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2398 | static int generic_enable_writeprotect(const struct flashctx *flash, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2399 | enum wp_mode wp_mode) |
| 2400 | { |
| 2401 | int ret; |
| 2402 | |
| 2403 | switch (wp_mode) { |
| 2404 | case WP_MODE_HARDWARE: |
| 2405 | ret = generic_set_srp0(flash, 1); |
| 2406 | break; |
| 2407 | default: |
| 2408 | msg_cerr("%s(): unsupported write-protect mode\n", __func__); |
| 2409 | return 1; |
| 2410 | } |
| 2411 | |
| 2412 | if (ret) |
| 2413 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 2414 | return ret; |
| 2415 | } |
| 2416 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2417 | static int generic_disable_writeprotect(const struct flashctx *flash) |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2418 | { |
| 2419 | int ret; |
| 2420 | |
| 2421 | ret = generic_set_srp0(flash, 0); |
| 2422 | if (ret) |
| 2423 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 2424 | return ret; |
| 2425 | } |
| 2426 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2427 | static int generic_list_ranges(const struct flashctx *flash) |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2428 | { |
| 2429 | struct generic_wp *wp; |
| 2430 | struct generic_range *r; |
| 2431 | int i, num_entries; |
| 2432 | |
| 2433 | if (generic_range_table(flash, &wp, &num_entries)) |
| 2434 | return -1; |
| 2435 | |
| 2436 | r = &wp->ranges[0]; |
| 2437 | for (i = 0; i < num_entries; i++) { |
| 2438 | msg_cinfo("start: 0x%06x, length: 0x%06x\n", |
| 2439 | r->range.start, r->range.len); |
| 2440 | r++; |
| 2441 | } |
| 2442 | |
| 2443 | return 0; |
| 2444 | } |
| 2445 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 2446 | static int generic_wp_status(const struct flashctx *flash) |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2447 | { |
| 2448 | uint8_t sr1; |
| 2449 | unsigned int start, len; |
| 2450 | int ret = 0; |
| 2451 | struct generic_wp *wp; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2452 | int num_entries, wp_en; |
| 2453 | |
| 2454 | if (generic_range_table(flash, &wp, &num_entries)) |
| 2455 | return -1; |
| 2456 | |
Ramya Vijaykumar | 4af3f82 | 2016-01-27 11:51:27 +0530 | [diff] [blame] | 2457 | sr1 = do_read_status(flash); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 2458 | wp_en = (sr1 >> wp->sr1.srp_pos) & 1; |
| 2459 | |
| 2460 | msg_cinfo("WP: status: 0x%04x\n", sr1); |
| 2461 | msg_cinfo("WP: status.srp0: %x\n", wp_en); |
| 2462 | /* FIXME: SRP1 is not really generic, but we probably should print |
| 2463 | * it anyway to have consistent output. #legacycruft */ |
| 2464 | msg_cinfo("WP: status.srp1: %x\n", 0); |
| 2465 | msg_cinfo("WP: write protect is %s.\n", |
| 2466 | wp_en ? "enabled" : "disabled"); |
| 2467 | |
| 2468 | msg_cinfo("WP: write protect range: "); |
| 2469 | if (generic_status_to_range(flash, sr1, &start, &len)) { |
| 2470 | msg_cinfo("(cannot resolve the range)\n"); |
| 2471 | ret = -1; |
| 2472 | } else { |
| 2473 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 2474 | } |
| 2475 | |
| 2476 | return ret; |
| 2477 | } |
| 2478 | |
| 2479 | struct wp wp_generic = { |
| 2480 | .list_ranges = generic_list_ranges, |
| 2481 | .set_range = generic_set_range, |
| 2482 | .enable = generic_enable_writeprotect, |
| 2483 | .disable = generic_disable_writeprotect, |
| 2484 | .wp_status = generic_wp_status, |
| 2485 | }; |