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stepan927d4e22007-04-04 22:45:58 +00001/*
uweb25f1ea2007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
stepan927d4e22007-04-04 22:45:58 +00003 *
uweb25f1ea2007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
uwe6ab4b7b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
wardfbe9c652007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
stepan927d4e22007-04-04 22:45:58 +00008 *
uweb25f1ea2007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
stepan927d4e22007-04-04 22:45:58 +000012 *
uweb25f1ea2007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
stepan927d4e22007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
stepan927d4e22007-04-04 22:45:58 +000027#include <string.h>
stepan927d4e22007-04-04 22:45:58 +000028#include "flash.h"
stepan927d4e22007-04-04 22:45:58 +000029
hailfinger324a9cc2010-05-26 01:45:41 +000030#if defined(__i386__) || defined(__x86_64__)
stuge04909772007-05-04 04:47:04 +000031/*
uwebe4477b2007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
stuge04909772007-05-04 04:47:04 +000033 */
stuge04909772007-05-04 04:47:04 +000034/* Enter extended functions */
stugeaa35d392009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
uwe23438a02007-05-03 10:09:23 +000036{
hailfingere1f062f2008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
stuge04909772007-05-04 04:47:04 +000039}
uwe23438a02007-05-03 10:09:23 +000040
stuge04909772007-05-04 04:47:04 +000041/* Leave extended functions */
stugeaa35d392009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
stuge04909772007-05-04 04:47:04 +000043{
hailfingere1f062f2008-05-22 13:22:45 +000044 OUTB(0xAA, port);
stuge04909772007-05-04 04:47:04 +000045}
uwe23438a02007-05-03 10:09:23 +000046
hailfinger7bac0e52009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
stuge04909772007-05-04 04:47:04 +000049{
hailfinger7bac0e52009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
stuge04909772007-05-04 04:47:04 +000052}
uwe23438a02007-05-03 10:09:23 +000053
hailfinger7bac0e52009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
stuge04909772007-05-04 04:47:04 +000055{
hailfinger7bac0e52009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
stuge04909772007-05-04 04:47:04 +000058}
uwe23438a02007-05-03 10:09:23 +000059
hailfinger7bac0e52009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
stuge04909772007-05-04 04:47:04 +000061{
rminnich6079a1c2007-10-12 21:22:40 +000062 uint8_t tmp;
uwe23438a02007-05-03 10:09:23 +000063
hailfinger7bac0e52009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
uwe23438a02007-05-03 10:09:23 +000067}
68
hailfingerc236f9e2009-12-22 23:42:04 +000069/* Not used yet. */
70#if 0
71static int enable_flash_decode_superio(void)
72{
73 int ret;
74 uint8_t tmp;
75
76 switch (superio.vendor) {
77 case SUPERIO_VENDOR_NONE:
78 ret = -1;
79 break;
80 case SUPERIO_VENDOR_ITE:
81 enter_conf_mode_ite(superio.port);
uwef6f94d42010-03-13 17:28:29 +000082 /* Enable flash mapping. Works for most old ITE style Super I/O. */
hailfingerc236f9e2009-12-22 23:42:04 +000083 tmp = sio_read(superio.port, 0x24);
84 tmp |= 0xfc;
85 sio_write(superio.port, 0x24, tmp);
86 exit_conf_mode_ite(superio.port);
87 ret = 0;
88 break;
89 default:
snelsone42c3802010-05-07 20:09:04 +000090 msg_pdbg("Unhandled Super I/O type!\n");
hailfingerc236f9e2009-12-22 23:42:04 +000091 ret = -1;
92 break;
93 }
94 return ret;
95}
96#endif
97
uwebe4477b2007-08-23 16:08:21 +000098/**
mkarcherb2505c02010-05-24 16:03:57 +000099 * SMSC FDC37B787: Raise GPIO50
100 */
uweeb26b6e2010-06-07 19:06:26 +0000101static int fdc37b787_gpio50_raise(uint16_t port)
mkarcherb2505c02010-05-24 16:03:57 +0000102{
103 uint8_t id, val;
104
105 OUTB(0x55, port); /* enter conf mode */
106 id = sio_read(port, 0x20);
107 if (id != 0x44) {
uweeb26b6e2010-06-07 19:06:26 +0000108 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
mkarcherb2505c02010-05-24 16:03:57 +0000109 OUTB(0xAA, port); /* leave conf mode */
110 return -1;
111 }
112
113 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
114
115 val = sio_read(port, 0xC8); /* GP50 */
116 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
117 {
uweeb26b6e2010-06-07 19:06:26 +0000118 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
mkarcherb2505c02010-05-24 16:03:57 +0000119 OUTB(0xAA, port);
120 return -1;
121 }
122
123 sio_mask(port, 0xF9, 0x01, 0x01);
124
125 OUTB(0xAA, port); /* Leave conf mode */
126 return 0;
127}
128
129/**
130 * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
131 */
uweeb26b6e2010-06-07 19:06:26 +0000132static int fdc37b787_gpio50_raise_3f0(void)
mkarcherb2505c02010-05-24 16:03:57 +0000133{
uweeb26b6e2010-06-07 19:06:26 +0000134 return fdc37b787_gpio50_raise(0x3f0);
mkarcherb2505c02010-05-24 16:03:57 +0000135}
136
mkarcher51455562010-06-27 15:07:49 +0000137struct winbond_mux {
138 uint8_t reg; /* 0 if the corresponding pin is not muxed */
139 uint8_t data; /* reg/data/mask may be directly ... */
140 uint8_t mask; /* ... passed to sio_mask */
141};
142
143struct winbond_port {
144 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
145 uint8_t ldn; /* LDN this GPIO register is located in */
146 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
147 the GPIO port */
148 uint8_t base; /* base register in that LDN for the port */
149};
150
151struct winbond_chip {
152 uint8_t device_id; /* reg 0x20 of the expected w83626x */
153 uint8_t gpio_port_count;
154 const struct winbond_port *port;
155};
156
157
158#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
159
160enum winbond_id {
161 WINBOND_W83627HF_ID = 0x52,
mkarcher65f85742010-06-27 15:07:52 +0000162 WINBOND_W83627EHF_ID = 0x88,
mkarcher51455562010-06-27 15:07:49 +0000163 WINBOND_W83627THF_ID = 0x82,
164};
165
166static const struct winbond_mux w83627hf_port2_mux[8] = {
167 {0x2A, 0x01, 0x01}, /* or MIDI */
168 {0x2B, 0x80, 0x80}, /* or SPI */
169 {0x2B, 0x40, 0x40}, /* or SPI */
170 {0x2B, 0x20, 0x20}, /* or power LED */
171 {0x2B, 0x10, 0x10}, /* or watchdog */
172 {0x2B, 0x08, 0x08}, /* or infra red */
173 {0x2B, 0x04, 0x04}, /* or infra red */
174 {0x2B, 0x03, 0x03} /* or IRQ1 input */
175};
176
177static const struct winbond_port w83627hf[3] = {
178 UNIMPLEMENTED_PORT,
179 {w83627hf_port2_mux, 0x08, 0, 0xF0},
180 UNIMPLEMENTED_PORT
181};
182
mkarcher65f85742010-06-27 15:07:52 +0000183static const struct winbond_mux w83627ehf_port2_mux[8] = {
184 {0x29, 0x06, 0x02}, /* or MIDI */
185 {0x29, 0x06, 0x02},
186 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
187 {0x24, 0x02, 0x00},
188 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
189 {0x2A, 0x01, 0x01},
190 {0x2A, 0x01, 0x01},
191 {0x2A, 0x01, 0x01}
192};
193
194static const struct winbond_port w83627ehf[6] = {
195 UNIMPLEMENTED_PORT,
196 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
197 UNIMPLEMENTED_PORT,
198 UNIMPLEMENTED_PORT,
199 UNIMPLEMENTED_PORT,
200 UNIMPLEMENTED_PORT
201};
202
mkarcher51455562010-06-27 15:07:49 +0000203static const struct winbond_mux w83627thf_port4_mux[8] = {
204 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
205 {0x2D, 0x02, 0x02}, /* or resume reset */
206 {0x2D, 0x04, 0x04}, /* or S3 input */
207 {0x2D, 0x08, 0x08}, /* or PSON# */
208 {0x2D, 0x10, 0x10}, /* or PWROK */
209 {0x2D, 0x20, 0x20}, /* or suspend LED */
210 {0x2D, 0x40, 0x40}, /* or panel switch input */
211 {0x2D, 0x80, 0x80} /* or panel switch output */
212};
213
214static const struct winbond_port w83627thf[5] = {
215 UNIMPLEMENTED_PORT, /* GPIO1 */
216 UNIMPLEMENTED_PORT, /* GPIO2 */
217 UNIMPLEMENTED_PORT, /* GPIO3 */
218 {w83627thf_port4_mux, 0x09, 1, 0xF4},
219 UNIMPLEMENTED_PORT /* GPIO5 */
220};
221
222static const struct winbond_chip winbond_chips[] = {
223 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
mkarcher65f85742010-06-27 15:07:52 +0000224 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
mkarcher51455562010-06-27 15:07:49 +0000225 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
226};
227
228/* Detects which Winbond Super I/O is responding at the given base
229 address, but takes no effort to make sure the chip is really a
230 Winbond Super I/O */
231
232static const struct winbond_chip * winbond_superio_detect(uint16_t base)
233{
234 uint8_t chipid;
235 const struct winbond_chip * chip = NULL;
236 int i;
237
238 w836xx_ext_enter(base);
239 chipid = sio_read(base, 0x20);
240 for (i = 0; i < ARRAY_SIZE(winbond_chips); i++)
241 if (winbond_chips[i].device_id == chipid)
242 {
243 chip = &winbond_chips[i];
244 break;
245 }
246
247 w836xx_ext_leave(base);
248 return chip;
249}
250
251/* The chipid parameter goes away as soon as we have Super I/O matching in the
252 board enable table. The call to winbond_superio_detect goes away as
253 soon as we have generic Super I/O detection code. */
254static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
255 int pin, int raise)
256{
257 const struct winbond_chip * chip = NULL;
258 const struct winbond_port * gpio;
259 int port = pin / 10;
260 int bit = pin % 10;
261
262 chip = winbond_superio_detect(base);
263 if (!chip) {
264 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
265 return -1;
266 }
mkarcher87ee57f2010-06-29 14:44:40 +0000267 if (chip->device_id != chipid) {
268 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
269 "expected %x\n", chip->device_id, chipid);
270 return -1;
271 }
mkarcher51455562010-06-27 15:07:49 +0000272 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
273 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
274 pin);
275 return -1;
276 }
277
278 gpio = &chip->port[port - 1];
279
280 if (gpio->ldn == 0) {
281 msg_perr("\nERROR: GPIO%d is not supported yet on this"
282 " winbond chip\n", port);
283 return -1;
284 }
285
286 w836xx_ext_enter(base);
287
288 /* Select logical device */
289 sio_write(base, 0x07, gpio->ldn);
290
291 /* Activate logical device. */
292 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
293
294 /* Select GPIO function of that pin */
295 if (gpio->mux && gpio->mux[bit].reg)
296 sio_mask(base, gpio->mux[bit].reg,
297 gpio->mux[bit].data, gpio->mux[bit].mask);
298
299 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* make pin output */
300 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
301 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
302
303 w836xx_ext_leave(base);
304
305 return 0;
306}
307
mkarcherb2505c02010-05-24 16:03:57 +0000308/**
uwebe4477b2007-08-23 16:08:21 +0000309 * Winbond W83627HF: Raise GPIO24.
stuge04909772007-05-04 04:47:04 +0000310 *
311 * Suited for:
uwebe4477b2007-08-23 16:08:21 +0000312 * - Agami Aruma
313 * - IWILL DK8-HTX
stepan927d4e22007-04-04 22:45:58 +0000314 */
mkarcher51455562010-06-27 15:07:49 +0000315static int w83627hf_gpio24_raise_2e()
stepan927d4e22007-04-04 22:45:58 +0000316{
mkarcher51455562010-06-27 15:07:49 +0000317 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
rminnich6079a1c2007-10-12 21:22:40 +0000318}
319
320/**
mkarcher65f85742010-06-27 15:07:52 +0000321 * Winbond W83627EHF: Raise GPIO24.
322 *
323 * Suited for:
324 * - Asus A8N VM CSM
325 */
326static int w83627ehf_gpio24_raise_2e()
327{
328 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1);
329}
330
331/**
mkarcher51455562010-06-27 15:07:49 +0000332 * Winbond W83627THF: Raise GPIO 44.
rminnich6079a1c2007-10-12 21:22:40 +0000333 *
334 * Suited for:
stugea1efa0e2008-07-21 17:48:40 +0000335 * - MSI K8T Neo2-F
rminnich6079a1c2007-10-12 21:22:40 +0000336 */
mkarcher51455562010-06-27 15:07:49 +0000337static int w83627thf_gpio44_raise_2e()
rminnich6079a1c2007-10-12 21:22:40 +0000338{
mkarcher51455562010-06-27 15:07:49 +0000339 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
rminnich6079a1c2007-10-12 21:22:40 +0000340}
341
mkarcher51455562010-06-27 15:07:49 +0000342/**
343 * Winbond W83627THF: Raise GPIO 44.
344 *
345 * Suited for:
346 * - MSI K8N Neo3
347 */
348static int w83627thf_gpio44_raise_4e()
stugea1efa0e2008-07-21 17:48:40 +0000349{
mkarcher51455562010-06-27 15:07:49 +0000350 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
rminnich6079a1c2007-10-12 21:22:40 +0000351}
uwe6ed6d952007-12-04 21:49:06 +0000352
uwebe4477b2007-08-23 16:08:21 +0000353/**
uwe6ab4b7b2009-05-09 14:26:04 +0000354 * w83627: Enable MEMW# and set ROM size to max.
stepan927d4e22007-04-04 22:45:58 +0000355 */
hailfinger7bac0e52009-05-25 23:26:50 +0000356static void w836xx_memw_enable(uint16_t port)
stepan927d4e22007-04-04 22:45:58 +0000357{
hailfinger7bac0e52009-05-25 23:26:50 +0000358 w836xx_ext_enter(port);
359 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
uwe6ab4b7b2009-05-09 14:26:04 +0000360 /* Enable MEMW# and set ROM size select to max. (4M). */
hailfinger7bac0e52009-05-25 23:26:50 +0000361 sio_mask(port, 0x24, 0x28, 0x28);
uwe6ab4b7b2009-05-09 14:26:04 +0000362 }
hailfinger7bac0e52009-05-25 23:26:50 +0000363 w836xx_ext_leave(port);
uwe6ab4b7b2009-05-09 14:26:04 +0000364}
365
366/**
libv53f58142009-12-23 00:54:26 +0000367 * Suited for:
368 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
369 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
370 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
371 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
372 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
uwe6ab4b7b2009-05-09 14:26:04 +0000373 */
uweeb26b6e2010-06-07 19:06:26 +0000374static int w836xx_memw_enable_2e(void)
uwe6ab4b7b2009-05-09 14:26:04 +0000375{
libv53f58142009-12-23 00:54:26 +0000376 w836xx_memw_enable(0x2E);
stepan927d4e22007-04-04 22:45:58 +0000377
libv53f58142009-12-23 00:54:26 +0000378 return 0;
uwe6ab4b7b2009-05-09 14:26:04 +0000379}
380
libv71e95f52010-01-20 14:45:07 +0000381/**
mkarchered00ee62010-03-21 13:36:20 +0000382 * Suited for:
383 * - Termtek TK-3370 (rev. 2.5b)
384 */
uweeb26b6e2010-06-07 19:06:26 +0000385static int w836xx_memw_enable_4e(void)
mkarchered00ee62010-03-21 13:36:20 +0000386{
387 w836xx_memw_enable(0x4E);
388
389 return 0;
390}
391
392/**
libv71e95f52010-01-20 14:45:07 +0000393 *
394 */
uweeb26b6e2010-06-07 19:06:26 +0000395static int it8705f_write_enable(uint8_t port)
libv71e95f52010-01-20 14:45:07 +0000396{
397 enter_conf_mode_ite(port);
398 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
399 exit_conf_mode_ite(port);
400
401 return 0;
402}
403
404/**
405 * Suited for:
406 * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
407 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
408 * - Elitegroup K7S6A: SiS745 + ITE IT8705F
409 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
410 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
411 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
412 *
uwef6f94d42010-03-13 17:28:29 +0000413 * The SIS950 Super I/O probably requires the same flash write enable.
libv71e95f52010-01-20 14:45:07 +0000414 */
uweeb26b6e2010-06-07 19:06:26 +0000415static int it8705f_write_enable_2e(void)
libv71e95f52010-01-20 14:45:07 +0000416{
uweeb26b6e2010-06-07 19:06:26 +0000417 return it8705f_write_enable(0x2e);
libv71e95f52010-01-20 14:45:07 +0000418}
libv53f58142009-12-23 00:54:26 +0000419
mkarcherb507b7b2010-02-27 18:35:54 +0000420static int pc87360_gpio_set(uint8_t gpio, int raise)
421{
422 static const int bankbase[] = {0, 4, 8, 10, 12};
423 int gpio_bank = gpio / 8;
424 int gpio_pin = gpio % 8;
425 uint16_t baseport;
uwef6f94d42010-03-13 17:28:29 +0000426 uint8_t id, val;
mkarcherb507b7b2010-02-27 18:35:54 +0000427
uwef6f94d42010-03-13 17:28:29 +0000428 if (gpio_bank > 4) {
snelsone42c3802010-05-07 20:09:04 +0000429 msg_perr("PC87360: Invalid GPIO %d\n", gpio);
mkarcherb507b7b2010-02-27 18:35:54 +0000430 return -1;
431 }
432
433 id = sio_read(0x2E, 0x20);
uwef6f94d42010-03-13 17:28:29 +0000434 if (id != 0xE1) {
snelsone42c3802010-05-07 20:09:04 +0000435 msg_perr("PC87360: unexpected ID %02x\n", id);
mkarcherb507b7b2010-02-27 18:35:54 +0000436 return -1;
437 }
438
uwef6f94d42010-03-13 17:28:29 +0000439 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */
mkarcherb507b7b2010-02-27 18:35:54 +0000440 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
uwef6f94d42010-03-13 17:28:29 +0000441 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
snelsone42c3802010-05-07 20:09:04 +0000442 msg_perr("PC87360: invalid GPIO base address %04x\n",
mkarcherb507b7b2010-02-27 18:35:54 +0000443 baseport);
444 return -1;
445 }
446 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */
uwef6f94d42010-03-13 17:28:29 +0000447 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
mkarcherb507b7b2010-02-27 18:35:54 +0000448 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */
449
450 val = INB(baseport + bankbase[gpio_bank]);
uwef6f94d42010-03-13 17:28:29 +0000451 if (raise)
mkarcherb507b7b2010-02-27 18:35:54 +0000452 val |= 1 << gpio_pin;
453 else
454 val &= ~(1 << gpio_pin);
455 OUTB(val, baseport + bankbase[gpio_bank]);
456
457 return 0;
458}
459
uwe6ab4b7b2009-05-09 14:26:04 +0000460/**
461 * VT823x: Set one of the GPIO pins.
462 */
libv53f58142009-12-23 00:54:26 +0000463static int via_vt823x_gpio_set(uint8_t gpio, int raise)
uwe6ab4b7b2009-05-09 14:26:04 +0000464{
libv53f58142009-12-23 00:54:26 +0000465 struct pci_dev *dev;
uwe6ab4b7b2009-05-09 14:26:04 +0000466 uint16_t base;
libvc89fddc2009-12-09 07:53:01 +0000467 uint8_t val, bit, offset;
uwe6ab4b7b2009-05-09 14:26:04 +0000468
libv53f58142009-12-23 00:54:26 +0000469 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
470 switch (dev->device_id) {
471 case 0x3177: /* VT8235 */
472 case 0x3227: /* VT8237R */
473 case 0x3337: /* VT8237A */
474 break;
475 default:
snelsone42c3802010-05-07 20:09:04 +0000476 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
libv53f58142009-12-23 00:54:26 +0000477 return -1;
478 }
479
libv785ec422009-06-19 13:53:59 +0000480 if ((gpio >= 12) && (gpio <= 15)) {
481 /* GPIO12-15 -> output */
482 val = pci_read_byte(dev, 0xE4);
483 val |= 0x10;
484 pci_write_byte(dev, 0xE4, val);
485 } else if (gpio == 9) {
486 /* GPIO9 -> Output */
487 val = pci_read_byte(dev, 0xE4);
488 val |= 0x20;
489 pci_write_byte(dev, 0xE4, val);
libvc89fddc2009-12-09 07:53:01 +0000490 } else if (gpio == 5) {
491 val = pci_read_byte(dev, 0xE4);
492 val |= 0x01;
493 pci_write_byte(dev, 0xE4, val);
libv785ec422009-06-19 13:53:59 +0000494 } else {
snelsone42c3802010-05-07 20:09:04 +0000495 msg_perr("\nERROR: "
uwe6ab4b7b2009-05-09 14:26:04 +0000496 "VT823x GPIO%02d is not implemented.\n", gpio);
libv53f58142009-12-23 00:54:26 +0000497 return -1;
uwef6641642007-05-09 10:17:44 +0000498 }
stepan927d4e22007-04-04 22:45:58 +0000499
uwe6ab4b7b2009-05-09 14:26:04 +0000500 /* We need the I/O Base Address for this board's flash enable. */
501 base = pci_read_word(dev, 0x88) & 0xff80;
502
libvc89fddc2009-12-09 07:53:01 +0000503 offset = 0x4C + gpio / 8;
504 bit = 0x01 << (gpio % 8);
505
506 val = INB(base + offset);
uwe6ab4b7b2009-05-09 14:26:04 +0000507 if (raise)
508 val |= bit;
509 else
510 val &= ~bit;
libvc89fddc2009-12-09 07:53:01 +0000511 OUTB(val, base + offset);
stepan927d4e22007-04-04 22:45:58 +0000512
uwef6641642007-05-09 10:17:44 +0000513 return 0;
stepan927d4e22007-04-04 22:45:58 +0000514}
515
uwebe4477b2007-08-23 16:08:21 +0000516/**
uwe3a3ab2f2010-03-25 23:18:41 +0000517 * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
stepan927d4e22007-04-04 22:45:58 +0000518 */
uweeb26b6e2010-06-07 19:06:26 +0000519static int via_vt823x_gpio5_raise(void)
stepan927d4e22007-04-04 22:45:58 +0000520{
libv53f58142009-12-23 00:54:26 +0000521 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
522 return via_vt823x_gpio_set(5, 1);
uwe6ab4b7b2009-05-09 14:26:04 +0000523}
524
525/**
mkarcher12e731f2010-06-12 17:27:44 +0000526 * Suited for VIA EPIA EK & N & NL.
libv785ec422009-06-19 13:53:59 +0000527 */
uweeb26b6e2010-06-07 19:06:26 +0000528static int via_vt823x_gpio9_raise(void)
libv785ec422009-06-19 13:53:59 +0000529{
libv53f58142009-12-23 00:54:26 +0000530 return via_vt823x_gpio_set(9, 1);
libv785ec422009-06-19 13:53:59 +0000531}
532
533/**
uwe3a3ab2f2010-03-25 23:18:41 +0000534 * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs.
libv53f58142009-12-23 00:54:26 +0000535 *
536 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
537 * lowered there.
uwe6ab4b7b2009-05-09 14:26:04 +0000538 */
uweeb26b6e2010-06-07 19:06:26 +0000539static int via_vt823x_gpio15_raise(void)
uwe6ab4b7b2009-05-09 14:26:04 +0000540{
libv53f58142009-12-23 00:54:26 +0000541 return via_vt823x_gpio_set(15, 1);
542}
543
544/**
545 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
546 *
547 * Suited for:
548 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
549 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
550 */
uweeb26b6e2010-06-07 19:06:26 +0000551static int board_msi_kt4v(void)
libv53f58142009-12-23 00:54:26 +0000552{
553 int ret;
554
555 ret = via_vt823x_gpio_set(12, 1);
uwe6ab4b7b2009-05-09 14:26:04 +0000556 w836xx_memw_enable(0x2E);
hailfinger755073f2008-02-09 02:03:06 +0000557
libv53f58142009-12-23 00:54:26 +0000558 return ret;
hailfinger755073f2008-02-09 02:03:06 +0000559}
560
561/**
uwe691ddb62007-05-20 16:16:13 +0000562 * Suited for ASUS P5A.
563 *
564 * This is rather nasty code, but there's no way to do this cleanly.
565 * We're basically talking to some unknown device on SMBus, my guess
566 * is that it is the Winbond W83781D that lives near the DIP BIOS.
567 */
uweeb26b6e2010-06-07 19:06:26 +0000568static int board_asus_p5a(void)
uwe691ddb62007-05-20 16:16:13 +0000569{
570 uint8_t tmp;
571 int i;
572
573#define ASUSP5A_LOOP 5000
574
hailfingere1f062f2008-05-22 13:22:45 +0000575 OUTB(0x00, 0xE807);
576 OUTB(0xEF, 0xE803);
uwe691ddb62007-05-20 16:16:13 +0000577
hailfingere1f062f2008-05-22 13:22:45 +0000578 OUTB(0xFF, 0xE800);
uwe691ddb62007-05-20 16:16:13 +0000579
580 for (i = 0; i < ASUSP5A_LOOP; i++) {
hailfingere1f062f2008-05-22 13:22:45 +0000581 OUTB(0xE1, 0xFF);
582 if (INB(0xE800) & 0x04)
uwe691ddb62007-05-20 16:16:13 +0000583 break;
584 }
585
586 if (i == ASUSP5A_LOOP) {
uweeb26b6e2010-06-07 19:06:26 +0000587 msg_perr("Unable to contact device.\n");
uwe691ddb62007-05-20 16:16:13 +0000588 return -1;
589 }
590
hailfingere1f062f2008-05-22 13:22:45 +0000591 OUTB(0x20, 0xE801);
592 OUTB(0x20, 0xE1);
uwe691ddb62007-05-20 16:16:13 +0000593
hailfingere1f062f2008-05-22 13:22:45 +0000594 OUTB(0xFF, 0xE802);
uwe691ddb62007-05-20 16:16:13 +0000595
596 for (i = 0; i < ASUSP5A_LOOP; i++) {
hailfingere1f062f2008-05-22 13:22:45 +0000597 tmp = INB(0xE800);
uwe691ddb62007-05-20 16:16:13 +0000598 if (tmp & 0x70)
599 break;
600 }
601
602 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
uweeb26b6e2010-06-07 19:06:26 +0000603 msg_perr("Failed to read device.\n");
uwe691ddb62007-05-20 16:16:13 +0000604 return -1;
605 }
606
hailfingere1f062f2008-05-22 13:22:45 +0000607 tmp = INB(0xE804);
uwe691ddb62007-05-20 16:16:13 +0000608 tmp &= ~0x02;
609
hailfingere1f062f2008-05-22 13:22:45 +0000610 OUTB(0x00, 0xE807);
611 OUTB(0xEE, 0xE803);
uwe691ddb62007-05-20 16:16:13 +0000612
hailfingere1f062f2008-05-22 13:22:45 +0000613 OUTB(tmp, 0xE804);
uwe691ddb62007-05-20 16:16:13 +0000614
hailfingere1f062f2008-05-22 13:22:45 +0000615 OUTB(0xFF, 0xE800);
616 OUTB(0xE1, 0xFF);
uwe691ddb62007-05-20 16:16:13 +0000617
hailfingere1f062f2008-05-22 13:22:45 +0000618 OUTB(0x20, 0xE801);
619 OUTB(0x20, 0xE1);
uwe691ddb62007-05-20 16:16:13 +0000620
hailfingere1f062f2008-05-22 13:22:45 +0000621 OUTB(0xFF, 0xE802);
uwe691ddb62007-05-20 16:16:13 +0000622
623 for (i = 0; i < ASUSP5A_LOOP; i++) {
hailfingere1f062f2008-05-22 13:22:45 +0000624 tmp = INB(0xE800);
uwe691ddb62007-05-20 16:16:13 +0000625 if (tmp & 0x70)
626 break;
627 }
628
629 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
uweeb26b6e2010-06-07 19:06:26 +0000630 msg_perr("Failed to write to device.\n");
uwe691ddb62007-05-20 16:16:13 +0000631 return -1;
632 }
633
634 return 0;
635}
636
libv6a74dbe2009-12-09 11:39:02 +0000637/*
638 * Set GPIO lines in the Broadcom HT-1000 southbridge.
639 *
640 * It's not a Super I/O but it uses the same index/data port method.
641 */
uweeb26b6e2010-06-07 19:06:26 +0000642static int board_hp_dl145_g3_enable(void)
libv6a74dbe2009-12-09 11:39:02 +0000643{
644 /* GPIO 0 reg from PM regs */
645 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
646 sio_mask(0xcd6, 0x44, 0x24, 0x24);
647
648 return 0;
649}
650
hailfinger08c281b2010-07-01 11:16:28 +0000651/*
652 * Set GPIO lines in the Broadcom HT-1000 southbridge.
653 *
654 * It's not a Super I/O but it uses the same index/data port method.
655 */
656static int board_hp_dl165_g6_enable(void)
657{
658 /* Variant of DL145, with slightly different pin placement. */
659 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
660 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
661
662 return 0;
663}
664
uweeb26b6e2010-06-07 19:06:26 +0000665static int board_ibm_x3455(void)
stepan60b4d872007-06-05 12:51:52 +0000666{
libv6a74dbe2009-12-09 11:39:02 +0000667 /* raise gpio13 */
hailfinger9c47a702009-06-01 21:30:42 +0000668 sio_mask(0xcd6, 0x45, 0x20, 0x20);
stepan60b4d872007-06-05 12:51:52 +0000669
670 return 0;
671}
672
libv5736b072009-06-03 07:50:39 +0000673/**
uwe3a3ab2f2010-03-25 23:18:41 +0000674 * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4).
libvb13ceec2009-10-21 12:05:50 +0000675 */
uweeb26b6e2010-06-07 19:06:26 +0000676static int board_shuttle_fn25(void)
libvb13ceec2009-10-21 12:05:50 +0000677{
678 struct pci_dev *dev;
679
680 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
681 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +0000682 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
libvb13ceec2009-10-21 12:05:50 +0000683 return -1;
684 }
685
686 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
687 pci_write_byte(dev, 0x92, 0);
688
689 return 0;
690}
691
692/**
libv6db37e62009-12-03 12:25:34 +0000693 * Very similar to AMD 8111 IO Hub.
libv5ac6e5c2009-10-05 16:07:00 +0000694 */
libv6db37e62009-12-03 12:25:34 +0000695static int nvidia_mcp_gpio_set(int gpio, int raise)
libv5ac6e5c2009-10-05 16:07:00 +0000696{
libv6db37e62009-12-03 12:25:34 +0000697 struct pci_dev *dev;
libv5ac6e5c2009-10-05 16:07:00 +0000698 uint16_t base;
mkarcherbb421582010-06-01 16:09:06 +0000699 uint16_t devclass;
libv5ac6e5c2009-10-05 16:07:00 +0000700 uint8_t tmp;
701
libv8068cf92009-12-22 13:04:13 +0000702 if ((gpio < 0) || (gpio >= 0x40)) {
snelsone42c3802010-05-07 20:09:04 +0000703 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
libv5736b072009-06-03 07:50:39 +0000704 return -1;
705 }
706
libv8068cf92009-12-22 13:04:13 +0000707 /* First, check the ISA Bridge */
708 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
libv6db37e62009-12-03 12:25:34 +0000709 switch (dev->device_id) {
710 case 0x0030: /* CK804 */
711 case 0x0050: /* MCP04 */
712 case 0x0060: /* MCP2 */
mkarcherd2189b42010-06-12 23:07:26 +0000713 case 0x00E0: /* CK8 */
libv6db37e62009-12-03 12:25:34 +0000714 break;
mkarcherbb421582010-06-01 16:09:06 +0000715 case 0x0260: /* MCP51 */
716 case 0x0364: /* MCP55 */
717 /* find SMBus controller on *this* southbridge */
718 /* The infamous Tyan S2915-E has two south bridges; they are
719 easily told apart from each other by the class of the
720 LPC bridge, but have the same SMBus bridge IDs */
721 if (dev->func != 0) {
722 msg_perr("MCP LPC bridge at unexpected function"
723 " number %d\n", dev->func);
724 return -1;
725 }
726
727 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
728 if (!dev) {
729 msg_perr("MCP SMBus controller could not be found\n");
730 return -1;
731 }
732 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
733 if (devclass != 0x0C05) {
734 msg_perr("Unexpected device class %04x for SMBus"
735 " controller\n", devclass);
736 return -1;
737 }
libv8068cf92009-12-22 13:04:13 +0000738 break;
mkarcherbb421582010-06-01 16:09:06 +0000739 default:
snelsone42c3802010-05-07 20:09:04 +0000740 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
libv6db37e62009-12-03 12:25:34 +0000741 return -1;
742 }
743
744 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
745 base += 0xC0;
746
747 tmp = INB(base + gpio);
748 tmp &= ~0x0F; /* null lower nibble */
749 tmp |= 0x04; /* gpio -> output. */
750 if (raise)
751 tmp |= 0x01;
752 OUTB(tmp, base + gpio);
libv5736b072009-06-03 07:50:39 +0000753
754 return 0;
755}
756
libv5ac6e5c2009-10-05 16:07:00 +0000757/**
snelsonedf5a882010-03-19 22:58:15 +0000758 * Suited for ASUS A8N-LA: nVidia MCP51.
uwe3a3ab2f2010-03-25 23:18:41 +0000759 * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51.
mkarcher28d6c872010-03-07 16:42:55 +0000760 */
uweeb26b6e2010-06-07 19:06:26 +0000761static int nvidia_mcp_gpio0_raise(void)
mkarcher28d6c872010-03-07 16:42:55 +0000762{
763 return nvidia_mcp_gpio_set(0x00, 1);
764}
765
766/**
snelsone1eaba92010-03-19 22:37:29 +0000767 * Suited for Abit KN8 Ultra: nVidia CK804.
768 */
uweeb26b6e2010-06-07 19:06:26 +0000769static int nvidia_mcp_gpio2_lower(void)
snelsone1eaba92010-03-19 22:37:29 +0000770{
771 return nvidia_mcp_gpio_set(0x02, 0);
772}
773
774/**
uwe3a3ab2f2010-03-25 23:18:41 +0000775 * Suited for MSI K8N Neo4: NVIDIA CK804.
776 * Suited for MSI K8N GM2-L: NVIDIA MCP51.
libv64ace522009-12-23 03:01:36 +0000777 */
uweeb26b6e2010-06-07 19:06:26 +0000778static int nvidia_mcp_gpio2_raise(void)
libv64ace522009-12-23 03:01:36 +0000779{
780 return nvidia_mcp_gpio_set(0x02, 1);
781}
782
mkarcherbb421582010-06-01 16:09:06 +0000783
784/**
785 * Suited for HP xw9400 (Tyan S2915-E OEM): Dual(!) nVidia MCP55.
786 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
787 * board. We can't tell the SMBus logical devices apart, but we
788 * can tell the LPC bridge functions apart.
789 * We need to choose the SMBus bridge next to the LPC bridge with
790 * ID 0x364 and the "LPC bridge" class.
791 * b) #TBL is hardwired on that board to a pull-down. It can be
792 * overridden by connecting the two solder points next to F2.
793 */
uweeb26b6e2010-06-07 19:06:26 +0000794static int nvidia_mcp_gpio5_raise(void)
mkarcherbb421582010-06-01 16:09:06 +0000795{
796 return nvidia_mcp_gpio_set(0x05, 1);
797}
798
libv64ace522009-12-23 03:01:36 +0000799/**
mkarcher8b7b04a2010-04-11 21:01:06 +0000800 * Suited for Abit NF7-S: NVIDIA CK804.
801 */
uweeb26b6e2010-06-07 19:06:26 +0000802static int nvidia_mcp_gpio8_raise(void)
mkarcher8b7b04a2010-04-11 21:01:06 +0000803{
804 return nvidia_mcp_gpio_set(0x08, 1);
805}
806
807/**
mkarcherd2189b42010-06-12 23:07:26 +0000808 * Suited for MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8.
809 */
mkarcherd291e752010-06-12 23:14:03 +0000810static int nvidia_mcp_gpio0c_raise(void)
mkarcherd2189b42010-06-12 23:07:26 +0000811{
812 return nvidia_mcp_gpio_set(0x0c, 1);
813}
814
815/**
libv5ac6e5c2009-10-05 16:07:00 +0000816 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
817 */
uweeb26b6e2010-06-07 19:06:26 +0000818static int nvidia_mcp_gpio10_raise(void)
libv5ac6e5c2009-10-05 16:07:00 +0000819{
libv6db37e62009-12-03 12:25:34 +0000820 return nvidia_mcp_gpio_set(0x10, 1);
821}
libv5ac6e5c2009-10-05 16:07:00 +0000822
libv6db37e62009-12-03 12:25:34 +0000823/**
824 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
825 */
uweeb26b6e2010-06-07 19:06:26 +0000826static int nvidia_mcp_gpio21_raise(void)
libv6db37e62009-12-03 12:25:34 +0000827{
828 return nvidia_mcp_gpio_set(0x21, 0x01);
libv5ac6e5c2009-10-05 16:07:00 +0000829}
830
libvb8043812009-10-05 18:46:35 +0000831/**
832 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
833 */
uweeb26b6e2010-06-07 19:06:26 +0000834static int nvidia_mcp_gpio31_raise(void)
libvb8043812009-10-05 18:46:35 +0000835{
libv6db37e62009-12-03 12:25:34 +0000836 return nvidia_mcp_gpio_set(0x31, 0x01);
libvb8043812009-10-05 18:46:35 +0000837}
libv5ac6e5c2009-10-05 16:07:00 +0000838
uwe0b88fc32007-08-11 16:59:11 +0000839/**
stepanf778f522008-02-20 11:11:18 +0000840 * Suited for Artec Group DBE61 and DBE62.
841 */
uweeb26b6e2010-06-07 19:06:26 +0000842static int board_artecgroup_dbe6x(void)
stepanf778f522008-02-20 11:11:18 +0000843{
844#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
845#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
846#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
847#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
848#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
849#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
850#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
851#define DBE6x_BOOT_LOC_FLASH (2)
852#define DBE6x_BOOT_LOC_FWHUB (3)
853
stepanf251ff82009-08-12 18:25:24 +0000854 msr_t msr;
stepanf778f522008-02-20 11:11:18 +0000855 unsigned long boot_loc;
856
stepanf251ff82009-08-12 18:25:24 +0000857 /* Geode only has a single core */
858 if (setup_cpu_msr(0))
stepanf778f522008-02-20 11:11:18 +0000859 return -1;
stepanf778f522008-02-20 11:11:18 +0000860
stepanf251ff82009-08-12 18:25:24 +0000861 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
stepanf778f522008-02-20 11:11:18 +0000862
stepanf251ff82009-08-12 18:25:24 +0000863 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
stepanf778f522008-02-20 11:11:18 +0000864 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
865 boot_loc = DBE6x_BOOT_LOC_FWHUB;
866 else
867 boot_loc = DBE6x_BOOT_LOC_FLASH;
868
stepanf251ff82009-08-12 18:25:24 +0000869 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
870 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
uwefa98ca12008-10-18 21:14:13 +0000871 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
stepanf778f522008-02-20 11:11:18 +0000872
stepanf251ff82009-08-12 18:25:24 +0000873 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
stepanf778f522008-02-20 11:11:18 +0000874
stepanf251ff82009-08-12 18:25:24 +0000875 cleanup_cpu_msr();
stepanf778f522008-02-20 11:11:18 +0000876
stepanf778f522008-02-20 11:11:18 +0000877 return 0;
878}
879
uwecc6ecc52008-05-22 21:19:38 +0000880/**
uwe3a3ab2f2010-03-25 23:18:41 +0000881 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
libv8d908612009-12-14 10:41:58 +0000882 */
883static int intel_piix4_gpo_set(unsigned int gpo, int raise)
884{
mkarcher681bc022010-02-24 00:00:21 +0000885 unsigned int gpo_byte, gpo_bit;
libv8d908612009-12-14 10:41:58 +0000886 struct pci_dev *dev;
887 uint32_t tmp, base;
888
889 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
890 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +0000891 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
libv8d908612009-12-14 10:41:58 +0000892 return -1;
893 }
894
895 /* sanity check */
896 if (gpo > 30) {
snelsone42c3802010-05-07 20:09:04 +0000897 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
libv8d908612009-12-14 10:41:58 +0000898 return -1;
899 }
900
901 /* these are dual function pins which are most likely in use already */
902 if (((gpo >= 1) && (gpo <= 7)) ||
903 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
snelsone42c3802010-05-07 20:09:04 +0000904 msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
libv8d908612009-12-14 10:41:58 +0000905 return -1;
906 }
907
908 /* dual function that need special enable. */
909 if ((gpo >= 22) && (gpo <= 26)) {
910 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
911 switch (gpo) {
912 case 22: /* XBUS: XDIR#/GPO22 */
913 case 23: /* XBUS: XOE#/GPO23 */
914 tmp |= 1 << 28;
915 break;
916 case 24: /* RTCSS#/GPO24 */
917 tmp |= 1 << 29;
918 break;
919 case 25: /* RTCALE/GPO25 */
920 tmp |= 1 << 30;
921 break;
922 case 26: /* KBCSS#/GPO26 */
923 tmp |= 1 << 31;
924 break;
925 }
926 pci_write_long(dev, 0xB0, tmp);
927 }
928
929 /* GPO {0,8,27,28,30} are always available. */
930
931 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
932 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +0000933 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
libv8d908612009-12-14 10:41:58 +0000934 return -1;
935 }
936
937 /* PM IO base */
938 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
939
mkarcher681bc022010-02-24 00:00:21 +0000940 gpo_byte = gpo >> 3;
941 gpo_bit = gpo & 7;
942 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
libv8d908612009-12-14 10:41:58 +0000943 if (raise)
mkarcher681bc022010-02-24 00:00:21 +0000944 tmp |= 0x01 << gpo_bit;
libv8d908612009-12-14 10:41:58 +0000945 else
mkarcher681bc022010-02-24 00:00:21 +0000946 tmp &= ~(0x01 << gpo_bit);
947 OUTB(tmp, base + 0x34 + gpo_byte);
libv8d908612009-12-14 10:41:58 +0000948
949 return 0;
950}
951
952/**
953 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
954 */
uweeb26b6e2010-06-07 19:06:26 +0000955static int board_epox_ep_bx3(void)
libv8d908612009-12-14 10:41:58 +0000956{
957 return intel_piix4_gpo_set(22, 1);
958}
959
960/**
snelsonaa2f3d92010-03-19 22:35:21 +0000961 * Suited for Intel SE440BX-2
962 */
uweeb26b6e2010-06-07 19:06:26 +0000963static int intel_piix4_gpo27_lower(void)
snelsonaa2f3d92010-03-19 22:35:21 +0000964{
965 return intel_piix4_gpo_set(27, 0);
966}
967
968/**
uwe3a3ab2f2010-03-25 23:18:41 +0000969 * Set a GPIO line on a given Intel ICH LPC controller.
uwecc6ecc52008-05-22 21:19:38 +0000970 */
libv5afe85c2009-11-28 18:07:51 +0000971static int intel_ich_gpio_set(int gpio, int raise)
uwecc6ecc52008-05-22 21:19:38 +0000972{
uwe3a3ab2f2010-03-25 23:18:41 +0000973 /* Table mapping the different Intel ICH LPC chipsets. */
libv5afe85c2009-11-28 18:07:51 +0000974 static struct {
975 uint16_t id;
976 uint8_t base_reg;
977 uint32_t bank0;
978 uint32_t bank1;
979 uint32_t bank2;
980 } intel_ich_gpio_table[] = {
981 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
982 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
983 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
984 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
985 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
986 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
987 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
988 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
989 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
990 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
991 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
992 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
993 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
994 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
995 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
996 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
997 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
998 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
999 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1000 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1001 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1002 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1003 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1004 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1005 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1006 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1007 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1008 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1009 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1010 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1011 {0, 0, 0, 0, 0} /* end marker */
1012 };
uwecc6ecc52008-05-22 21:19:38 +00001013
libv5afe85c2009-11-28 18:07:51 +00001014 struct pci_dev *dev;
1015 uint16_t base;
1016 uint32_t tmp;
1017 int i, allowed;
1018
1019 /* First, look for a known LPC bridge */
hailfingerd9bfbe22009-12-14 04:24:42 +00001020 for (dev = pacc->devices; dev; dev = dev->next) {
hailfinger2b8fc0b2010-05-21 23:00:56 +00001021 uint16_t device_class;
1022 /* libpci before version 2.2.4 does not store class info. */
1023 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
libv5afe85c2009-11-28 18:07:51 +00001024 if ((dev->vendor_id == 0x8086) &&
hailfinger2b8fc0b2010-05-21 23:00:56 +00001025 (device_class == 0x0601)) { /* ISA Bridge */
libv5afe85c2009-11-28 18:07:51 +00001026 /* Is this device in our list? */
1027 for (i = 0; intel_ich_gpio_table[i].id; i++)
1028 if (dev->device_id == intel_ich_gpio_table[i].id)
1029 break;
1030
1031 if (intel_ich_gpio_table[i].id)
1032 break;
1033 }
hailfingerd9bfbe22009-12-14 04:24:42 +00001034 }
libv5afe85c2009-11-28 18:07:51 +00001035
uwecc6ecc52008-05-22 21:19:38 +00001036 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +00001037 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
uwecc6ecc52008-05-22 21:19:38 +00001038 return -1;
1039 }
1040
uwe3a3ab2f2010-03-25 23:18:41 +00001041 /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1042 strapped to zero. From some mobile ICH9 version on, this becomes
libv5afe85c2009-11-28 18:07:51 +00001043 6:1. The mask below catches all. */
1044 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
uwecc6ecc52008-05-22 21:19:38 +00001045
libv5afe85c2009-11-28 18:07:51 +00001046 /* check whether the line is allowed */
1047 if (gpio < 32)
1048 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1049 else if (gpio < 64)
1050 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1051 else
1052 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1053
1054 if (!allowed) {
snelsone42c3802010-05-07 20:09:04 +00001055 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
libv5afe85c2009-11-28 18:07:51 +00001056 " setting GPIO%02d\n", gpio);
1057 return -1;
1058 }
1059
snelsone42c3802010-05-07 20:09:04 +00001060 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
libv5afe85c2009-11-28 18:07:51 +00001061 raise ? "Rais" : "Dropp", gpio);
1062
1063 if (gpio < 32) {
1064 /* Set line to GPIO */
1065 tmp = INL(base);
1066 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1067 if ((gpio == 28) &&
1068 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1069 tmp |= 1 << 27;
1070 else
1071 tmp |= 1 << gpio;
1072 OUTL(tmp, base);
1073
1074 /* As soon as we are talking to ICH8 and above, this register
1075 decides whether we can set the gpio or not. */
1076 if (dev->device_id > 0x2800) {
1077 tmp = INL(base);
1078 if (!(tmp & (1 << gpio))) {
snelsone42c3802010-05-07 20:09:04 +00001079 msg_perr("\nERROR: This Intel LPC Bridge"
libv5afe85c2009-11-28 18:07:51 +00001080 " does not allow setting GPIO%02d\n",
1081 gpio);
1082 return -1;
1083 }
1084 }
1085
1086 /* Set GPIO to OUTPUT */
1087 tmp = INL(base + 0x04);
1088 tmp &= ~(1 << gpio);
1089 OUTL(tmp, base + 0x04);
1090
1091 /* Raise GPIO line */
1092 tmp = INL(base + 0x0C);
1093 if (raise)
1094 tmp |= 1 << gpio;
1095 else
1096 tmp &= ~(1 << gpio);
1097 OUTL(tmp, base + 0x0C);
1098 } else if (gpio < 64) {
1099 gpio -= 32;
1100
1101 /* Set line to GPIO */
1102 tmp = INL(base + 0x30);
1103 tmp |= 1 << gpio;
1104 OUTL(tmp, base + 0x30);
1105
1106 /* As soon as we are talking to ICH8 and above, this register
1107 decides whether we can set the gpio or not. */
1108 if (dev->device_id > 0x2800) {
1109 tmp = INL(base + 30);
1110 if (!(tmp & (1 << gpio))) {
snelsone42c3802010-05-07 20:09:04 +00001111 msg_perr("\nERROR: This Intel LPC Bridge"
libv5afe85c2009-11-28 18:07:51 +00001112 " does not allow setting GPIO%02d\n",
1113 gpio + 32);
1114 return -1;
1115 }
1116 }
1117
1118 /* Set GPIO to OUTPUT */
1119 tmp = INL(base + 0x34);
1120 tmp &= ~(1 << gpio);
1121 OUTL(tmp, base + 0x34);
1122
1123 /* Raise GPIO line */
1124 tmp = INL(base + 0x38);
1125 if (raise)
1126 tmp |= 1 << gpio;
1127 else
1128 tmp &= ~(1 << gpio);
1129 OUTL(tmp, base + 0x38);
1130 } else {
1131 gpio -= 64;
1132
1133 /* Set line to GPIO */
1134 tmp = INL(base + 0x40);
1135 tmp |= 1 << gpio;
1136 OUTL(tmp, base + 0x40);
1137
1138 tmp = INL(base + 40);
1139 if (!(tmp & (1 << gpio))) {
snelsone42c3802010-05-07 20:09:04 +00001140 msg_perr("\nERROR: This Intel LPC Bridge does "
libv5afe85c2009-11-28 18:07:51 +00001141 "not allow setting GPIO%02d\n", gpio + 64);
1142 return -1;
1143 }
1144
1145 /* Set GPIO to OUTPUT */
1146 tmp = INL(base + 0x44);
1147 tmp &= ~(1 << gpio);
1148 OUTL(tmp, base + 0x44);
1149
1150 /* Raise GPIO line */
1151 tmp = INL(base + 0x48);
1152 if (raise)
1153 tmp |= 1 << gpio;
1154 else
1155 tmp &= ~(1 << gpio);
1156 OUTL(tmp, base + 0x48);
1157 }
uwecc6ecc52008-05-22 21:19:38 +00001158
1159 return 0;
1160}
1161
1162/**
libv5afe85c2009-11-28 18:07:51 +00001163 * Suited for Abit IP35: Intel P35 + ICH9R.
mkarcherfa18d3a2010-03-03 16:15:12 +00001164 * Suited for Abit IP35 Pro: Intel P35 + ICH9R.
uwecc6ecc52008-05-22 21:19:38 +00001165 */
uweeb26b6e2010-06-07 19:06:26 +00001166static int intel_ich_gpio16_raise(void)
uwecc6ecc52008-05-22 21:19:38 +00001167{
libv5afe85c2009-11-28 18:07:51 +00001168 return intel_ich_gpio_set(16, 1);
uwecc6ecc52008-05-22 21:19:38 +00001169}
1170
stuge81664dd2009-02-02 22:55:26 +00001171/**
snelson0a9016e2010-03-19 22:39:24 +00001172 * Suited for ASUS A8JM: Intel 945 + ICH7
1173 */
uweeb26b6e2010-06-07 19:06:26 +00001174static int intel_ich_gpio34_raise(void)
snelson0a9016e2010-03-19 22:39:24 +00001175{
1176 return intel_ich_gpio_set(34, 1);
1177}
1178
1179/**
libv5afe85c2009-11-28 18:07:51 +00001180 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
hailfinger3fa8d842009-09-23 02:05:12 +00001181 */
uweeb26b6e2010-06-07 19:06:26 +00001182static int intel_ich_gpio19_raise(void)
hailfinger3fa8d842009-09-23 02:05:12 +00001183{
libv5afe85c2009-11-28 18:07:51 +00001184 return intel_ich_gpio_set(19, 1);
hailfinger3fa8d842009-09-23 02:05:12 +00001185}
1186
1187/**
libvdc84fa32009-11-28 18:26:21 +00001188 * Suited for:
uwe3a3ab2f2010-03-25 23:18:41 +00001189 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
1190 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5.
1191 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
stuge81664dd2009-02-02 22:55:26 +00001192 */
uweeb26b6e2010-06-07 19:06:26 +00001193static int intel_ich_gpio21_raise(void)
stuge81664dd2009-02-02 22:55:26 +00001194{
libv5afe85c2009-11-28 18:07:51 +00001195 return intel_ich_gpio_set(21, 1);
stuge81664dd2009-02-02 22:55:26 +00001196}
1197
libv5afe85c2009-11-28 18:07:51 +00001198/**
mkarcher11f8f3c2010-03-07 16:32:32 +00001199 * Suited for:
uwe3a3ab2f2010-03-25 23:18:41 +00001200 * - ASUS P4B266: socket478 + Intel 845D + ICH2.
1201 * - ASUS P4B533-E: socket478 + 845E + ICH4
1202 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
libv5afe85c2009-11-28 18:07:51 +00001203 */
uweeb26b6e2010-06-07 19:06:26 +00001204static int intel_ich_gpio22_raise(void)
libv5afe85c2009-11-28 18:07:51 +00001205{
1206 return intel_ich_gpio_set(22, 1);
1207}
1208
1209/**
mkarcherb507b7b2010-02-27 18:35:54 +00001210 * Suited for HP Vectra VL400: 815 + ICH + PC87360.
1211 */
1212
uweeb26b6e2010-06-07 19:06:26 +00001213static int board_hp_vl400(void)
mkarcherb507b7b2010-02-27 18:35:54 +00001214{
1215 int ret;
1216 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1217 if (!ret)
1218 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
1219 if (!ret)
1220 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
1221 return ret;
1222}
1223
1224/**
libve42a7c62009-11-28 18:16:31 +00001225 * Suited for:
uwe3a3ab2f2010-03-25 23:18:41 +00001226 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R.
libve42a7c62009-11-28 18:16:31 +00001227 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
libv5afe85c2009-11-28 18:07:51 +00001228 */
uweeb26b6e2010-06-07 19:06:26 +00001229static int intel_ich_gpio23_raise(void)
libv5afe85c2009-11-28 18:07:51 +00001230{
1231 return intel_ich_gpio_set(23, 1);
1232}
1233
1234/**
snelson4e249922010-03-19 23:01:34 +00001235 * Suited for IBase MB899: i945GM + ICH7.
1236 */
uweeb26b6e2010-06-07 19:06:26 +00001237static int intel_ich_gpio26_raise(void)
snelson4e249922010-03-19 23:01:34 +00001238{
1239 return intel_ich_gpio_set(26, 1);
1240}
1241
1242/**
libv5afe85c2009-11-28 18:07:51 +00001243 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
1244 */
uweeb26b6e2010-06-07 19:06:26 +00001245static int board_acorp_6a815epd(void)
libv5afe85c2009-11-28 18:07:51 +00001246{
1247 int ret;
1248
1249 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1250 ret = intel_ich_gpio_set(22, 1);
1251 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1252 ret = intel_ich_gpio_set(23, 1);
1253
1254 return ret;
1255}
1256
1257/**
1258 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
1259 */
uweeb26b6e2010-06-07 19:06:26 +00001260static int board_kontron_986lcd_m(void)
stepanb8361b92008-03-17 22:59:40 +00001261{
libv5afe85c2009-11-28 18:07:51 +00001262 int ret;
stepanb8361b92008-03-17 22:59:40 +00001263
libv5afe85c2009-11-28 18:07:51 +00001264 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1265 if (!ret)
1266 ret = intel_ich_gpio_set(35, 1); /* #WP */
stepanb8361b92008-03-17 22:59:40 +00001267
libv5afe85c2009-11-28 18:07:51 +00001268 return ret;
stepanb8361b92008-03-17 22:59:40 +00001269}
1270
stepanf778f522008-02-20 11:11:18 +00001271/**
libv88cd3d22009-06-17 14:43:24 +00001272 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1273 */
snelsonef86df92010-03-19 22:49:09 +00001274static int via_apollo_gpo_set(int gpio, int raise)
libv88cd3d22009-06-17 14:43:24 +00001275{
snelsonef86df92010-03-19 22:49:09 +00001276 struct pci_dev *dev;
libv88cd3d22009-06-17 14:43:24 +00001277 uint32_t base;
snelsonef86df92010-03-19 22:49:09 +00001278 uint32_t tmp;
libv88cd3d22009-06-17 14:43:24 +00001279
1280 /* VT82C686 Power management */
1281 dev = pci_dev_find(0x1106, 0x3057);
1282 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +00001283 msg_perr("\nERROR: VT82C686 PM device not found.\n");
libv88cd3d22009-06-17 14:43:24 +00001284 return -1;
1285 }
1286
snelsone42c3802010-05-07 20:09:04 +00001287 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
snelsonef86df92010-03-19 22:49:09 +00001288 raise ? "Rais" : "Dropp", gpio);
1289
1290 /* select GPO function on multiplexed pins */
libv88cd3d22009-06-17 14:43:24 +00001291 tmp = pci_read_byte(dev, 0x54);
snelsonef86df92010-03-19 22:49:09 +00001292 switch(gpio)
1293 {
1294 case 0:
1295 tmp &= ~0x03;
1296 break;
1297 case 1:
1298 tmp |= 0x04;
1299 break;
1300 case 2:
1301 tmp |= 0x08;
1302 break;
1303 case 3:
1304 tmp |= 0x10;
1305 break;
1306 }
libv88cd3d22009-06-17 14:43:24 +00001307 pci_write_byte(dev, 0x54, tmp);
1308
1309 /* PM IO base */
1310 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1311
1312 /* Drop GPO0 */
snelsonef86df92010-03-19 22:49:09 +00001313 tmp = INL(base + 0x4C);
1314 if (raise)
1315 tmp |= 1U << gpio;
1316 else
1317 tmp &= ~(1U << gpio);
1318 OUTL(tmp, base + 0x4C);
libv88cd3d22009-06-17 14:43:24 +00001319
1320 return 0;
1321}
1322
mkarchercd460642010-01-09 17:36:06 +00001323/**
mkarchera95f8882010-03-24 22:55:56 +00001324 * Suited for Abit VT6X4: Pro133x + VT82C686A
snelsone52df7d2010-03-19 22:30:49 +00001325 */
uweeb26b6e2010-06-07 19:06:26 +00001326static int via_apollo_gpo4_lower(void)
snelsone52df7d2010-03-19 22:30:49 +00001327{
1328 return via_apollo_gpo_set(4, 0);
1329}
1330
1331/**
snelsonef86df92010-03-19 22:49:09 +00001332 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1333 */
uweeb26b6e2010-06-07 19:06:26 +00001334static int via_apollo_gpo0_lower(void)
snelsonef86df92010-03-19 22:49:09 +00001335{
1336 return via_apollo_gpo_set(0, 0);
1337}
1338
1339/**
mkarchercd460642010-01-09 17:36:06 +00001340 * Enable some GPIO pin on SiS southbridge.
1341 * Suited for MSI 651M-L: SiS651 / SiS962
1342 */
uweeb26b6e2010-06-07 19:06:26 +00001343static int board_msi_651ml(void)
mkarchercd460642010-01-09 17:36:06 +00001344{
1345 struct pci_dev *dev;
uwef6f94d42010-03-13 17:28:29 +00001346 uint16_t base, temp;
mkarchercd460642010-01-09 17:36:06 +00001347
1348 dev = pci_dev_find(0x1039, 0x0962);
1349 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +00001350 msg_perr("Expected south bridge not found\n");
mkarchercd460642010-01-09 17:36:06 +00001351 return 1;
1352 }
1353
1354 /* Registers 68 and 64 seem like bitmaps */
1355 base = pci_read_word(dev, 0x74);
1356 temp = INW(base + 0x68);
1357 temp &= ~(1 << 0); /* Make pin output? */
mkarcherc9602fb2010-01-09 23:31:13 +00001358 OUTW(temp, base + 0x68);
mkarchercd460642010-01-09 17:36:06 +00001359
1360 temp = INW(base + 0x64);
1361 temp |= (1 << 0); /* Raise output? */
1362 OUTW(temp, base + 0x64);
1363
1364 w836xx_memw_enable(0x2E);
1365
1366 return 0;
1367}
1368
libv88cd3d22009-06-17 14:43:24 +00001369/**
libv5bcbdea2009-06-19 13:00:24 +00001370 * Find the runtime registers of an SMSC Super I/O, after verifying its
1371 * chip ID.
1372 *
1373 * Returns the base port of the runtime register block, or 0 on error.
1374 */
1375static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1376 uint8_t logical_device)
1377{
1378 uint16_t rt_port = 0;
1379
1380 /* Verify the chip ID. */
uwe619a15a2009-06-28 23:26:37 +00001381 OUTB(0x55, sio_port); /* Enable configuration. */
libv5bcbdea2009-06-19 13:00:24 +00001382 if (sio_read(sio_port, 0x20) != chip_id) {
snelsone42c3802010-05-07 20:09:04 +00001383 msg_perr("\nERROR: SMSC Super I/O not found.\n");
libv5bcbdea2009-06-19 13:00:24 +00001384 goto out;
1385 }
1386
1387 /* If the runtime block is active, get its address. */
1388 sio_write(sio_port, 0x07, logical_device);
1389 if (sio_read(sio_port, 0x30) & 1) {
1390 rt_port = (sio_read(sio_port, 0x60) << 8)
1391 | sio_read(sio_port, 0x61);
1392 }
1393
1394 if (rt_port == 0) {
snelsone42c3802010-05-07 20:09:04 +00001395 msg_perr("\nERROR: "
libv5bcbdea2009-06-19 13:00:24 +00001396 "Super I/O runtime interface not available.\n");
1397 }
1398out:
uwe619a15a2009-06-28 23:26:37 +00001399 OUTB(0xaa, sio_port); /* Disable configuration. */
libv5bcbdea2009-06-19 13:00:24 +00001400 return rt_port;
1401}
1402
1403/**
1404 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
1405 * connected to GP30 on the Super I/O, and TBL# is always high.
1406 */
uweeb26b6e2010-06-07 19:06:26 +00001407static int board_mitac_6513wu(void)
libv5bcbdea2009-06-19 13:00:24 +00001408{
1409 struct pci_dev *dev;
1410 uint16_t rt_port;
1411 uint8_t val;
1412
1413 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1414 if (!dev) {
snelsone42c3802010-05-07 20:09:04 +00001415 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
libv5bcbdea2009-06-19 13:00:24 +00001416 return -1;
1417 }
1418
uwe619a15a2009-06-28 23:26:37 +00001419 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
libv5bcbdea2009-06-19 13:00:24 +00001420 if (rt_port == 0)
1421 return -1;
1422
1423 /* Configure the GPIO pin. */
1424 val = INB(rt_port + 0x33); /* GP30 config */
uwe619a15a2009-06-28 23:26:37 +00001425 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
libv5bcbdea2009-06-19 13:00:24 +00001426 OUTB(val, rt_port + 0x33);
1427
1428 /* Disable write protection. */
1429 val = INB(rt_port + 0x4d); /* GP3 values */
uwe619a15a2009-06-28 23:26:37 +00001430 val |= 0x01; /* Set GP30 high. */
libv5bcbdea2009-06-19 13:00:24 +00001431 OUTB(val, rt_port + 0x4d);
1432
1433 return 0;
1434}
1435
1436/**
uwe3a3ab2f2010-03-25 23:18:41 +00001437 * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A
libv1569a562009-07-13 12:40:17 +00001438 */
uweeb26b6e2010-06-07 19:06:26 +00001439static int board_asus_a7v8x(void)
libv1569a562009-07-13 12:40:17 +00001440{
1441 uint16_t id, base;
1442 uint8_t tmp;
1443
1444 /* find the IT8703F */
1445 w836xx_ext_enter(0x2E);
1446 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1447 w836xx_ext_leave(0x2E);
1448
1449 if (id != 0x8701) {
snelsone42c3802010-05-07 20:09:04 +00001450 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
libv1569a562009-07-13 12:40:17 +00001451 return -1;
1452 }
1453
1454 /* Get the GP567 IO base */
1455 w836xx_ext_enter(0x2E);
1456 sio_write(0x2E, 0x07, 0x0C);
1457 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1458 w836xx_ext_leave(0x2E);
1459
1460 if (!base) {
snelsone42c3802010-05-07 20:09:04 +00001461 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
libv1569a562009-07-13 12:40:17 +00001462 " Base.\n");
1463 return -1;
1464 }
1465
1466 /* Raise GP51. */
1467 tmp = INB(base);
1468 tmp |= 0x02;
1469 OUTB(tmp, base);
1470
1471 return 0;
1472}
1473
libv9c4d2b22009-09-01 21:22:23 +00001474/*
1475 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1476 * There is only some limited checking on the port numbers.
1477 */
uwef6f94d42010-03-13 17:28:29 +00001478static int it8712f_gpio_set(unsigned int line, int raise)
libv9c4d2b22009-09-01 21:22:23 +00001479{
1480 unsigned int port;
1481 uint16_t id, base;
1482 uint8_t tmp;
1483
1484 port = line / 10;
1485 port--;
1486 line %= 10;
1487
1488 /* Check line */
1489 if ((port > 4) || /* also catches unsigned -1 */
1490 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
snelsone42c3802010-05-07 20:09:04 +00001491 msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
libv9c4d2b22009-09-01 21:22:23 +00001492 return -1;
1493 }
1494
1495 /* find the IT8712F */
1496 enter_conf_mode_ite(0x2E);
1497 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1498 exit_conf_mode_ite(0x2E);
1499
1500 if (id != 0x8712) {
snelsone42c3802010-05-07 20:09:04 +00001501 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
libv9c4d2b22009-09-01 21:22:23 +00001502 return -1;
1503 }
1504
1505 /* Get the GPIO base */
1506 enter_conf_mode_ite(0x2E);
1507 sio_write(0x2E, 0x07, 0x07);
1508 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1509 exit_conf_mode_ite(0x2E);
1510
1511 if (!base) {
snelsone42c3802010-05-07 20:09:04 +00001512 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
libv9c4d2b22009-09-01 21:22:23 +00001513 " Base.\n");
1514 return -1;
1515 }
1516
1517 /* set GPIO. */
1518 tmp = INB(base + port);
1519 if (raise)
1520 tmp |= 1 << line;
1521 else
1522 tmp &= ~(1 << line);
1523 OUTB(tmp, base + port);
1524
1525 return 0;
1526}
1527
1528/**
mkarchercccf1392010-03-09 16:57:06 +00001529 * Suited for:
uwe3a3ab2f2010-03-25 23:18:41 +00001530 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1531 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
libv9c4d2b22009-09-01 21:22:23 +00001532 */
uweeb26b6e2010-06-07 19:06:26 +00001533static int it8712f_gpio3_1_raise(void)
libv9c4d2b22009-09-01 21:22:23 +00001534{
1535 return it8712f_gpio_set(32, 1);
1536}
1537
hailfinger324a9cc2010-05-26 01:45:41 +00001538#endif
1539
libv1569a562009-07-13 12:40:17 +00001540/**
uwec0751f42009-10-06 13:00:00 +00001541 * Below is the list of boards which need a special "board enable" code in
1542 * flashrom before their ROM chip can be accessed/written to.
1543 *
1544 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1545 * to the respective tables in print.c. Thanks!
1546 *
uwebe4477b2007-08-23 16:08:21 +00001547 * We use 2 sets of IDs here, you're free to choose which is which. This
1548 * is to provide a very high degree of certainty when matching a board on
1549 * the basis of subsystem/card IDs. As not every vendor handles
1550 * subsystem/card IDs in a sane manner.
stepan927d4e22007-04-04 22:45:58 +00001551 *
stuge84659842009-04-20 12:38:17 +00001552 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
hailfinger7fcb5b72010-02-04 11:12:04 +00001553 * NULLed if they don't identify the board fully and if you can't use DMI.
1554 * But please take care to provide an as complete set of pci ids as possible;
1555 * autodetection is the preferred behaviour and we would like to make sure that
1556 * matches are unique.
stepanf778f522008-02-20 11:11:18 +00001557 *
mkarcher803b4042010-01-20 14:14:11 +00001558 * If PCI IDs are not sufficient for board matching, the match can be further
1559 * constrained by a string that has to be present in the DMI database for
uwe3a3ab2f2010-03-25 23:18:41 +00001560 * the baseboard or the system entry. The pattern is matched by case sensitive
mkarcher803b4042010-01-20 14:14:11 +00001561 * substring match, unless it is anchored to the beginning (with a ^ in front)
1562 * or the end (with a $ at the end). Both anchors may be specified at the
1563 * same time to match the full field.
1564 *
hailfinger7fcb5b72010-02-04 11:12:04 +00001565 * When a board is matched through DMI, the first and second main PCI IDs
1566 * and the first subsystem PCI ID have to match as well. If you specify the
1567 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1568 * subsystem ID of that device is indeed zero.
1569 *
stuge84659842009-04-20 12:38:17 +00001570 * The coreboot ids are used two fold. When running with a coreboot firmware,
1571 * the ids uniquely matches the coreboot board identification string. When a
1572 * legacy bios is installed and when autodetection is not possible, these ids
1573 * can be used to identify the board through the -m command line argument.
1574 *
1575 * When a board is identified through its coreboot ids (in both cases), the
1576 * main pci ids are still required to match, as a safeguard.
stepan927d4e22007-04-04 22:45:58 +00001577 */
stepan927d4e22007-04-04 22:45:58 +00001578
uwec7f7eda2009-05-08 16:23:34 +00001579/* Please keep this list alphabetically ordered by vendor/board name. */
stepan927d4e22007-04-04 22:45:58 +00001580struct board_pciid_enable board_pciid_enables[] = {
uwe869efa02009-06-21 20:50:22 +00001581
mkarcherf2620582010-02-28 01:33:48 +00001582 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
hailfinger324a9cc2010-05-26 01:45:41 +00001583#if defined(__i386__) || defined(__x86_64__)
snelsone1061102010-03-19 23:00:07 +00001584 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
mkarcherf2620582010-02-28 01:33:48 +00001585 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
mkarcherfa18d3a2010-03-03 16:15:12 +00001586 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
snelsone1eaba92010-03-19 22:37:29 +00001587 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
mkarcher8b7b04a2010-04-11 21:01:06 +00001588 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
mkarchera95f8882010-03-24 22:55:56 +00001589 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
mkarcherf2620582010-02-28 01:33:48 +00001590 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
mkarcherf2620582010-02-28 01:33:48 +00001591 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
uwea161c972010-05-26 22:29:51 +00001592 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
mkarcherf2620582010-02-28 01:33:48 +00001593 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e},
1594 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1595 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
uwee6dc3012010-05-26 22:26:44 +00001596 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
mkarchercccf1392010-03-09 16:57:06 +00001597 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
uwee6dc3012010-05-26 22:26:44 +00001598 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
mkarcherf2620582010-02-28 01:33:48 +00001599 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
mkarchercccf1392010-03-09 16:57:06 +00001600 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
snelson0a9016e2010-03-19 22:39:24 +00001601 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise},
snelsonedf5a882010-03-19 22:58:15 +00001602 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise},
uwee6dc3012010-05-26 22:26:44 +00001603 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25},
mkarcher65f85742010-06-27 15:07:52 +00001604 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio24_raise_2e},
mkarcher28d6c872010-03-07 16:42:55 +00001605 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
mkarcherf2620582010-02-28 01:33:48 +00001606 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
mkarcherf2620582010-02-28 01:33:48 +00001607 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
uwee6dc3012010-05-26 22:26:44 +00001608 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
snelson933d4b02010-03-19 22:52:00 +00001609 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
mkarcher4c718632010-03-17 06:19:23 +00001610 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
mkarcherf2620582010-02-28 01:33:48 +00001611 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
1612 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
1613 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
1614 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e},
1615 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
1616 {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e},
1617 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e},
1618 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
1619 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
1620 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
mkarcherf2620582010-02-28 01:33:48 +00001621 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e},
uwee6dc3012010-05-26 22:26:44 +00001622 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
mkarcherf2620582010-02-28 01:33:48 +00001623 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
hailfinger08c281b2010-07-01 11:16:28 +00001624 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1625 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable},
mkarcherf2620582010-02-28 01:33:48 +00001626 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
mkarcher11f8f3c2010-03-07 16:32:32 +00001627 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
mkarcherbb421582010-06-01 16:09:06 +00001628 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
snelson4e249922010-03-19 23:01:34 +00001629 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise},
mkarcherf2620582010-02-28 01:33:48 +00001630 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1631 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
snelsonaa2f3d92010-03-19 22:35:21 +00001632 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
mkarcherf2620582010-02-28 01:33:48 +00001633 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
snelson0a9016e2010-03-19 22:39:24 +00001634 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
mkarcherf2620582010-02-28 01:33:48 +00001635 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
uwee6dc3012010-05-26 22:26:44 +00001636 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise},
mkarcherf2620582010-02-28 01:33:48 +00001637 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
mkarcher51455562010-06-27 15:07:49 +00001638 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
mkarcherf2620582010-02-28 01:33:48 +00001639 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
1640 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
mkarcherd2189b42010-06-12 23:07:26 +00001641 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
mkarcherf2620582010-02-28 01:33:48 +00001642 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
mkarcher51455562010-06-27 15:07:49 +00001643 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
mkarcher5de1c772010-03-07 16:52:59 +00001644 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
mkarcherb2505c02010-05-24 16:03:57 +00001645 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
mkarcherf2620582010-02-28 01:33:48 +00001646 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
1647 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e},
1648 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
snelsonef86df92010-03-19 22:49:09 +00001649 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
mkarcherf2620582010-02-28 01:33:48 +00001650 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
mkarchered00ee62010-03-21 13:36:20 +00001651 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
uwee6dc3012010-05-26 22:26:44 +00001652 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
mkarcher12e731f2010-06-12 17:27:44 +00001653 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
mkarcherf2620582010-02-28 01:33:48 +00001654 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1655 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
hailfinger324a9cc2010-05-26 01:45:41 +00001656#endif
mkarcherf2620582010-02-28 01:33:48 +00001657 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
stepan927d4e22007-04-04 22:45:58 +00001658};
1659
uwebe4477b2007-08-23 16:08:21 +00001660/**
stepan1037f6f2008-01-18 15:33:10 +00001661 * Match boards on coreboot table gathered vendor and part name.
uwebe4477b2007-08-23 16:08:21 +00001662 * Require main PCI IDs to match too as extra safety.
stepan927d4e22007-04-04 22:45:58 +00001663 */
uwefa98ca12008-10-18 21:14:13 +00001664static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1665 const char *part)
stepan927d4e22007-04-04 22:45:58 +00001666{
uwef6641642007-05-09 10:17:44 +00001667 struct board_pciid_enable *board = board_pciid_enables;
stugeb9b411f2008-01-27 16:21:21 +00001668 struct board_pciid_enable *partmatch = NULL;
stepan927d4e22007-04-04 22:45:58 +00001669
uwe4b650af2009-05-09 00:47:04 +00001670 for (; board->vendor_name; board++) {
uwefa98ca12008-10-18 21:14:13 +00001671 if (vendor && (!board->lb_vendor
1672 || strcasecmp(board->lb_vendor, vendor)))
uwef6641642007-05-09 10:17:44 +00001673 continue;
stepan927d4e22007-04-04 22:45:58 +00001674
stuge0c1005b2008-07-02 00:47:30 +00001675 if (!board->lb_part || strcasecmp(board->lb_part, part))
uwef6641642007-05-09 10:17:44 +00001676 continue;
stepan927d4e22007-04-04 22:45:58 +00001677
uwef6641642007-05-09 10:17:44 +00001678 if (!pci_dev_find(board->first_vendor, board->first_device))
1679 continue;
stepan927d4e22007-04-04 22:45:58 +00001680
uwef6641642007-05-09 10:17:44 +00001681 if (board->second_vendor &&
uwefa98ca12008-10-18 21:14:13 +00001682 !pci_dev_find(board->second_vendor, board->second_device))
uwef6641642007-05-09 10:17:44 +00001683 continue;
stugeb9b411f2008-01-27 16:21:21 +00001684
1685 if (vendor)
1686 return board;
1687
1688 if (partmatch) {
1689 /* a second entry has a matching part name */
snelsone42c3802010-05-07 20:09:04 +00001690 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
1691 msg_pinfo("At least vendors '%s' and '%s' match.\n",
uwefa98ca12008-10-18 21:14:13 +00001692 partmatch->lb_vendor, board->lb_vendor);
snelsone42c3802010-05-07 20:09:04 +00001693 msg_perr("Please use the full -m vendor:part syntax.\n");
stugeb9b411f2008-01-27 16:21:21 +00001694 return NULL;
1695 }
1696 partmatch = board;
uwef6641642007-05-09 10:17:44 +00001697 }
uwe6ed6d952007-12-04 21:49:06 +00001698
stugeb9b411f2008-01-27 16:21:21 +00001699 if (partmatch)
1700 return partmatch;
1701
stepan3370c892009-07-30 13:30:17 +00001702 if (!partvendor_from_cbtable) {
1703 /* Only warn if the mainboard type was not gathered from the
1704 * coreboot table. If it was, the coreboot implementor is
1705 * expected to fix flashrom, too.
1706 */
snelsone42c3802010-05-07 20:09:04 +00001707 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
stepan3370c892009-07-30 13:30:17 +00001708 vendor, part);
1709 }
uwef6641642007-05-09 10:17:44 +00001710 return NULL;
stepan927d4e22007-04-04 22:45:58 +00001711}
1712
uwebe4477b2007-08-23 16:08:21 +00001713/**
1714 * Match boards on PCI IDs and subsystem IDs.
1715 * Second set of IDs can be main only or missing completely.
stepan927d4e22007-04-04 22:45:58 +00001716 */
1717static struct board_pciid_enable *board_match_pci_card_ids(void)
1718{
uwef6641642007-05-09 10:17:44 +00001719 struct board_pciid_enable *board = board_pciid_enables;
stepan927d4e22007-04-04 22:45:58 +00001720
uwe4b650af2009-05-09 00:47:04 +00001721 for (; board->vendor_name; board++) {
mkarcher58fbded2010-02-04 10:58:50 +00001722 if ((!board->first_card_vendor || !board->first_card_device) &&
1723 !board->dmi_pattern)
uwef6641642007-05-09 10:17:44 +00001724 continue;
stepan927d4e22007-04-04 22:45:58 +00001725
uwef6641642007-05-09 10:17:44 +00001726 if (!pci_card_find(board->first_vendor, board->first_device,
uwefa98ca12008-10-18 21:14:13 +00001727 board->first_card_vendor,
1728 board->first_card_device))
uwef6641642007-05-09 10:17:44 +00001729 continue;
stepan927d4e22007-04-04 22:45:58 +00001730
uwef6641642007-05-09 10:17:44 +00001731 if (board->second_vendor) {
1732 if (board->second_card_vendor) {
1733 if (!pci_card_find(board->second_vendor,
uwefa98ca12008-10-18 21:14:13 +00001734 board->second_device,
1735 board->second_card_vendor,
1736 board->second_card_device))
uwef6641642007-05-09 10:17:44 +00001737 continue;
1738 } else {
1739 if (!pci_dev_find(board->second_vendor,
uwefa98ca12008-10-18 21:14:13 +00001740 board->second_device))
uwef6641642007-05-09 10:17:44 +00001741 continue;
1742 }
1743 }
stepan927d4e22007-04-04 22:45:58 +00001744
mkarcher803b4042010-01-20 14:14:11 +00001745 if (board->dmi_pattern) {
1746 if (!has_dmi_support) {
snelsone42c3802010-05-07 20:09:04 +00001747 msg_perr("WARNING: Can't autodetect %s %s,"
mkarcher803b4042010-01-20 14:14:11 +00001748 " DMI info unavailable.\n",
1749 board->vendor_name, board->board_name);
1750 continue;
1751 } else {
1752 if (!dmi_match(board->dmi_pattern))
1753 continue;
1754 }
1755 }
1756
uwef6641642007-05-09 10:17:44 +00001757 return board;
1758 }
stepan927d4e22007-04-04 22:45:58 +00001759
uwef6641642007-05-09 10:17:44 +00001760 return NULL;
stepan927d4e22007-04-04 22:45:58 +00001761}
1762
uwe6ed6d952007-12-04 21:49:06 +00001763int board_flash_enable(const char *vendor, const char *part)
stepan927d4e22007-04-04 22:45:58 +00001764{
uwef6641642007-05-09 10:17:44 +00001765 struct board_pciid_enable *board = NULL;
1766 int ret = 0;
stepan927d4e22007-04-04 22:45:58 +00001767
stugeb9b411f2008-01-27 16:21:21 +00001768 if (part)
stepan1037f6f2008-01-18 15:33:10 +00001769 board = board_match_coreboot_name(vendor, part);
stepan927d4e22007-04-04 22:45:58 +00001770
uwef6641642007-05-09 10:17:44 +00001771 if (!board)
1772 board = board_match_pci_card_ids();
stepan927d4e22007-04-04 22:45:58 +00001773
mkarchera0488b92010-03-11 23:04:16 +00001774 if (board && board->status == NT) {
uwef6f94d42010-03-13 17:28:29 +00001775 if (!force_boardenable) {
snelsone42c3802010-05-07 20:09:04 +00001776 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
mkarcher29a80852010-03-07 22:29:28 +00001777 "code has not been tested, and thus will not not be executed by default.\n"
1778 "Depending on your hardware environment, erasing, writing or even probing\n"
1779 "can fail without running the board specific code.\n\n"
1780 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
uwef6f94d42010-03-13 17:28:29 +00001781 "\"internal programmer\") for details.\n",
mkarcher29a80852010-03-07 22:29:28 +00001782 board->vendor_name, board->board_name);
1783 board = NULL;
uwef6f94d42010-03-13 17:28:29 +00001784 } else {
snelsone42c3802010-05-07 20:09:04 +00001785 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
uwef6f94d42010-03-13 17:28:29 +00001786 "Please report success/failure to flashrom@flashrom.org.\n");
1787 }
mkarcher29a80852010-03-07 22:29:28 +00001788 }
1789
uwef6641642007-05-09 10:17:44 +00001790 if (board) {
libve9b336e2010-01-20 14:45:03 +00001791 if (board->max_rom_decode_parallel)
1792 max_rom_decode.parallel =
1793 board->max_rom_decode_parallel * 1024;
1794
uwe0ec24c22010-01-28 19:02:36 +00001795 if (board->enable != NULL) {
snelsone42c3802010-05-07 20:09:04 +00001796 msg_pinfo("Disabling flash write protection for "
uwe0ec24c22010-01-28 19:02:36 +00001797 "board \"%s %s\"... ", board->vendor_name,
1798 board->board_name);
stepan927d4e22007-04-04 22:45:58 +00001799
uweeb26b6e2010-06-07 19:06:26 +00001800 ret = board->enable();
uwe0ec24c22010-01-28 19:02:36 +00001801 if (ret)
snelsone42c3802010-05-07 20:09:04 +00001802 msg_pinfo("FAILED!\n");
uwe0ec24c22010-01-28 19:02:36 +00001803 else
snelsone42c3802010-05-07 20:09:04 +00001804 msg_pinfo("OK.\n");
uwe0ec24c22010-01-28 19:02:36 +00001805 }
uwef6641642007-05-09 10:17:44 +00001806 }
stepan927d4e22007-04-04 22:45:58 +00001807
uwef6641642007-05-09 10:17:44 +00001808 return ret;
stepan927d4e22007-04-04 22:45:58 +00001809}