tree:/ Switch to FLAG based 4ba support for spi chips
This attempts to reland the previous commit
9997445971cd7df721db228deac6dd3309039458
The following chips are impacted by removing the callback
and instead leaning on the chip feature flag to determine
when to enter_exit out of 4ba modes;
- GD25Q256D
- MX25L25635F/MX25L25645G
- W25Q256.V
- W25Q256JV_M
Slight difference with upstream in that we validate
(flash->chip->bustype == BUS_SPI) as ich copies the
chip flags in the opaque master and tries incorrectly
to issue 4BA commands which results in failure.
BUG=b:170690915,b:178419441,b:177252170
BRANCH=none
TEST=tested on 32MB Puff.
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: Ia353f88ed366532a5d99b23c6ff12fe8dbe9feb2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2532333
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: Sam McNally <sammc@chromium.org>
Reviewed-by: Sam McNally <sammc@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit-Queue: Edward O'Callaghan <quasisec@chromium.org>
diff --git a/flashrom.c b/flashrom.c
index 1755857..e94fc12 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -2349,6 +2349,20 @@
}
}
+ /* Enable/disable 4-byte addressing mode if flash chip supports it */
+ if ((flash->chip->bustype == BUS_SPI) &&
+ (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7))) {
+ int ret;
+ if (spi_master_4ba(flash))
+ ret = spi_enter_4ba(flash);
+ else
+ ret = spi_exit_4ba(flash);
+ if (ret) {
+ msg_cerr("Failed to set correct 4BA mode! Aborting.\n");
+ return 1;
+ }
+ }
+
return 0;
}