Massive integration with upstream code. This brings us up from 1130 to 1235.
Most merges trivial (or near-trivial):
- Some print statements were adjusted to reduce verbosity.
- Partial update logic in flashrom.c changed to use upstream version.
- handle_romentries prototype from flash.h updated.
- updated chip ID entries in writeprotect.c
There is one UI change:
UI change: --wp-range on AGZ platform with Nuvoton EC no longer does --wp-enable implicitly. User should specify both --wp-range and --wp-enable using the same command on the CLI.
Minor code changes:
- Made it so that chip commands (set_wp_*) are not mutually exclusive with each other in cli_mfg.c. This allows us to set a write-protect range and enable write protection simultaneously. This was helpful for wpce775x changes (below).
WPCE775x code was completely re-factored to be a programmer instead of a chip. This was required to make it work with the new partial write logic. Here are the wpce775x.c changes:
Forward-ported the code to integrate with Flashrom more now that Flashrom has generic core routines for partial updates and such. This has the pleasant side-effect of simplifying the code and allowing us to trivially support a broad range of flash chips.
The updated flow is:
- internal_init() calls wpce775x_probe_* commands. Probing and WCB setup are done here. EC enters "update" mode (even if EC content is not being changed)
- Flashrom chip detect logic issues RDID command. The "flash" struct is determined with the corresponding flash chip..
- When read/write/erase/write protect functions are called, InitFlash() sets up WCB with appropriate chip parameters.
- wpce775x_shutdown() exits flash update mode.
Summary of wpce775x changes:
- Implemented SPI --> WCB translation interface.
- Switch over to using Flashrom's built-in partial write logic.
- Simplify WPCE775x probe/init routines. Since Flashrom will handle chip
detection by using the SPI --> WCB interface, we can remove chip-specific
stuff. Also, probe_wpce775x is now known as wpce775x_spi_common_init.
- Update all read, write, erase, and write-protect options with the ability
to support any SPI chip. This is done by allowing each function to change
WCB parameters on-the-fly using InitFlash().
(note: tested two different erase methods by forcing usage of either 4K or
64k erase block sizes)
- Remove wp_wpce775x struct; we no longer need it. We will use write protect
protect functions are provided for the detected chip (in writeprotect.c).
- Make in_flash_update_mode a boolean rather than a counter. When we do write protect changes we need to force the sequence: InitFlash(), EnterFlashUpdate(), ExitFlashUpdateFirmwareNoChange(). Using a counter
caused EnterFlashUpdate() and ExitFlashUpdateFirmwareNoChange() to abort prematurely.
Tested on:
Mario AGZ Alex
partial_writes_x86_bios PASS PASS PASS
partial_writes_ec PASS* PASS N/A
wp-range (bios) PASS PASS FAIL**
wp-range (ec) PASS PASS*** N/A
wp-toggle (bios) PASS PASS FAIL**
wp-toggle (ec) PASS PASS***
get-size (bios) PASS PASS FAIL**
get-size (ec) PASS PASS N/A
* - Tested on prototype hardware due to too small EC firmware ROM size of PVT machine.
** - Got weird bash error (probably due to "untested chip" spew). Will fix in follow-up.
*** - Can't test with script (due to EC not supporting "read status register" command), tested with Dediprog
Highlights from upstream include:
r1232: Reversible PCI config space write functions (rpci_* functions) which automatically add a shutdown callback to "undo" changes.
r1226, r1227: Improved Dediprog SF100 support
r1224: Use "real partial writes" for all chips.
r1223: Fix semantics of layout.
r1220 and r1218: Added SPI flash chip emulator and torture script, which ought to greatly improve testing.
r1217: Fix internal offset calculation for SPI byte program and AAI program, allowing us to start at non-zero offsets.
r1215: Always read chip before writing, and skip erase/writing of blocks that do not need to change.
r1211: Switch all chips to use partial write.
r1208: Refactor all write functions to use the form:
int write(struct flashchip *flash, uint8_t *src, int start, int len);
r1206: Kill programmer/chip specific erase functions, call erase from generic
code instead.
r1201: Add polling for completion of SPI write status register operation
r1193: On-the-fly reprogramming of ICH SPI opcode table
r1181, r1186: Improved DOS support
r1172: Add a delay to allow chips to exit ID mode before proceding with other
operations.
r1171: Improved SPI bitbanging support
r1170: Honor ICH SPI addres window for reads
r1147, r1148, r1149, r1150: Add FEATURE_WRSR_WREN to feature_bits for Eon,
Amic, Macronix, and Winbond SPI chips.
Review URL: http://codereview.appspot.com/2539041
diff --git a/programmer.h b/programmer.h
index bbe24f9..303f3b4 100644
--- a/programmer.h
+++ b/programmer.h
@@ -37,10 +37,10 @@
#if CONFIG_NICREALTEK == 1
PROGRAMMER_NICREALTEK,
PROGRAMMER_NICREALTEK2,
-#endif
+#endif
#if CONFIG_NICNATSEMI == 1
PROGRAMMER_NICNATSEMI,
-#endif
+#endif
#if CONFIG_GFXNVIDIA == 1
PROGRAMMER_GFXNVIDIA,
#endif
@@ -73,6 +73,9 @@
#if CONFIG_RAYER_SPI == 1
PROGRAMMER_RAYER_SPI,
#endif
+#if CONFIG_NICINTEL_SPI == 1
+ PROGRAMMER_NICINTEL_SPI,
+#endif
PROGRAMMER_INVALID /* This must always be the last entry. */
};
@@ -110,6 +113,9 @@
#if CONFIG_RAYER_SPI == 1
BITBANG_SPI_MASTER_RAYER,
#endif
+#if CONFIG_NICINTEL_SPI == 1
+ BITBANG_SPI_MASTER_NICINTEL,
+#endif
#if CONFIG_INTERNAL == 1
#if defined(__i386__) || defined(__x86_64__)
BITBANG_SPI_MASTER_MCP,
@@ -125,6 +131,8 @@
void (*set_sck) (int val);
void (*set_mosi) (int val);
int (*get_miso) (void);
+ void (*request_bus) (void);
+ void (*release_bus) (void);
};
#if CONFIG_INTERNAL == 1
@@ -204,10 +212,16 @@
};
uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs);
uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs);
+/* rpci_write_* are reversible writes. The original PCI config space register
+ * contents will be restored on shutdown.
+ */
+int rpci_write_byte(struct pci_dev *dev, int reg, u8 data);
+int rpci_write_word(struct pci_dev *dev, int reg, u16 data);
+int rpci_write_long(struct pci_dev *dev, int reg, u32 data);
#endif
/* print.c */
-#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1
+#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI >= 1
void print_supported_pcidevs(const struct pcidev_status *devs);
#endif
@@ -378,6 +392,16 @@
extern const struct pcidev_status nics_natsemi[];
#endif
+/* nicintel_spi.c */
+#if CONFIG_NICINTEL_SPI == 1
+int nicintel_spi_init(void);
+int nicintel_spi_shutdown(void);
+int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
+void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr);
+extern const struct pcidev_status nics_intel_spi[];
+#endif
+
/* satasii.c */
#if CONFIG_SATASII == 1
int satasii_init(void);
@@ -399,11 +423,11 @@
/* ft2232_spi.c */
#if CONFIG_FT2232_SPI == 1
struct usbdev_status {
-uint16_t vendor_id;
- uint16_t device_id;
- int status;
- const char *vendor_name;
- const char *device_name;
+ uint16_t vendor_id;
+ uint16_t device_id;
+ int status;
+ const char *vendor_name;
+ const char *device_name;
};
int ft2232_spi_init(void);
int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
@@ -427,6 +451,7 @@
/* bitbang_spi.c */
int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
+int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
@@ -447,6 +472,7 @@
int dediprog_shutdown(void);
int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
+int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
/* flashrom.c */
struct decode_sizes {
@@ -478,6 +504,7 @@
SPI_CONTROLLER_VIA,
SPI_CONTROLLER_WBSIO,
SPI_CONTROLLER_MCP6X_BITBANG,
+ SPI_CONTROLLER_WPCE775X,
#endif
#endif
#if CONFIG_FT2232_SPI == 1
@@ -495,6 +522,9 @@
#if CONFIG_RAYER_SPI == 1
SPI_CONTROLLER_RAYER,
#endif
+#if CONFIG_NICINTEL_SPI == 1
+ SPI_CONTROLLER_NICINTEL,
+#endif
SPI_CONTROLLER_INVALID /* This must always be the last entry. */
};
extern const int spi_programmer_count;
@@ -578,6 +608,18 @@
typedef int fdtype;
#endif
+/* wpce775x.c */
+struct superio probe_superio_wpce775x(void);
+int wpce775x_shutdown(void);
+int wpce775x_probe_spi_flash(const char *name);
+int wpce775x_spi_read(struct flashchip *flash,
+ uint8_t * buf, int start, int len);
+int wpce775x_spi_write_256(struct flashchip *flash,
+ uint8_t *buf, int start, int len);
+int wpce775x_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr,
+ unsigned char *readarr);
+
void sp_flush_incoming(void);
fdtype sp_openserport(char *dev, unsigned int baud);
void __attribute__((noreturn)) sp_die(char *msg);