programmer.c,h: Sync with upstream
BUG=none
BRANCH=none
TEST=none
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: Ic548f35fb22924ba494452061f58516c597834f0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2554668
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Commit-Queue: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@chromium.org>
Auto-Submit: Edward O'Callaghan <quasisec@chromium.org>
diff --git a/programmer.c b/programmer.c
index 8c5946d..476be0c 100644
--- a/programmer.c
+++ b/programmer.c
@@ -42,19 +42,14 @@
{
}
-/* No-op chip_writeb() for drivers not supporting addr/data pair accesses */
-uint8_t noop_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
- return 0xff;
-}
-
-/* No-op chip_writeb() for drivers not supporting addr/data pair accesses */
+/* No-op chip_writeb() for parallel style drivers not supporting writes */
void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
{
}
/* Little-endian fallback for drivers not supporting 16 bit accesses */
-void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr)
+void fallback_chip_writew(const struct flashctx *flash, uint16_t val,
+ chipaddr addr)
{
chip_writeb(flash, val & 0xff, addr);
chip_writeb(flash, (val >> 8) & 0xff, addr + 1);
@@ -70,7 +65,8 @@
}
/* Little-endian fallback for drivers not supporting 32 bit accesses */
-void fallback_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr)
+void fallback_chip_writel(const struct flashctx *flash, uint32_t val,
+ chipaddr addr)
{
chip_writew(flash, val & 0xffff, addr);
chip_writew(flash, (val >> 16) & 0xffff, addr + 2);
@@ -93,7 +89,8 @@
return;
}
-void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, chipaddr addr, size_t len)
+void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf,
+ chipaddr addr, size_t len)
{
size_t i;
for (i = 0; i < len; i++)