Check ICH erase command support at run time.
When deciding which erasers should be used for a certain flashrom
session, one needs to take into account the fact that Intel SPI
controller (included in the ICH) could be allowing only a subset of
erase commands supported by the flash chip.
Instead of hardcoding the susbsets of supported commands let's
introduce the 'dry run' mode, where the command is invoked and
verified by the ICH driver, but actual action is not taken.
The nonzero return code indicates that a command is not supported by
the controller.
Note that ICH support should be verified only when programming the
main AP flash, ICH is not involved when programming the EC.
BRANCH=none
BUG=b:862703
TEST=verified that previously failing tests succeed on auron and cyan.
On auron, cyan and eve verified that reprogramming flash spaces
of 4K, 16K, 32K, 64K and 128K bytes works as expected.
Change-Id: Ifa248c9d42c28c644373fb28ec6a3d710211c228
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1139405
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/programmer.h b/programmer.h
index 71da8e4..880e9cd 100644
--- a/programmer.h
+++ b/programmer.h
@@ -107,6 +107,14 @@
extern struct programmer_alias *alias;
extern struct programmer_alias aliases[];
+/*
+ * This function returns 'true' if current flashrom invocation is programming
+ * the EC.
+ */
+static inline int programming_ec(void) {
+ return alias && (alias->type == ALIAS_EC);
+}
+
struct programmer_entry {
const char *vendor;
const char *name;
@@ -610,7 +618,16 @@
* device. When running on non-intel platforms default value of
* CHIPSET_ICH_UNKNOWN is used.
*/
-enum ich_chipset ich_generation;
+extern enum ich_chipset ich_generation;
+
+/*
+ * This global variable is set to indicate that the invoked flash programming
+ * command should not be executed, but just verified for validity.
+ *
+ * This is useful when one needs to determine if a certain flash erase command
+ * supported by the chip is allowed by the Intel controller on the device.
+ */
+extern int ich_dry_run;
extern uint32_t ichspi_bbar;
int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
enum ich_chipset ich_generation);