Makefile: enforce target name in generated dependencies
Due to the current ccache version's bug need to explicitly request gcc
to set the generated .d file's targets to include the path to the .o
file.
BUG=b:148943341
TEST=verified that relevant object files are rebuilt when an .h file
is touched.
Change-Id: Ifbe48c191f8585f40da4eac1db29c44f4686c5c3
diff --git a/Makefile b/Makefile
index 393969a..3a5b54b 100644
--- a/Makefile
+++ b/Makefile
@@ -52,7 +52,8 @@
$(obj)/%.d $(obj)/%.o: %.c | $(obj)
@echo " CC $(notdir $<)"
- $(Q)$(CC) $(CFLAGS) -c -MMD -MF $(basename $@).d -o $(basename $@).o $<
+ $(Q)$(CC) $(CFLAGS) -c -MMD -MF $(basename $@).d -MT $(basename $@).o \
+ -o $(basename $@).o $<
.PHONY: clean
clean: