soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blob
BUG=b:173653085
TEST=Stress pass
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ia565eab885033a0398e2f988d56a73b90f6b1323
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/blobs/+/2517305
Reviewed-by: Yu-Ping Wu <yupingso@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
diff --git a/soc/mediatek/mt8192/dpm.dm b/soc/mediatek/mt8192/dpm.dm
index 8ace902..dada9cb 100755
--- a/soc/mediatek/mt8192/dpm.dm
+++ b/soc/mediatek/mt8192/dpm.dm
Binary files differ
diff --git a/soc/mediatek/mt8192/dpm.pm b/soc/mediatek/mt8192/dpm.pm
index 306953c..064ff55 100755
--- a/soc/mediatek/mt8192/dpm.pm
+++ b/soc/mediatek/mt8192/dpm.pm
Binary files differ
diff --git a/soc/mediatek/mt8192/dpm_release_notes.txt b/soc/mediatek/mt8192/dpm_release_notes.txt
index 5a9a721..6822e61 100644
--- a/soc/mediatek/mt8192/dpm_release_notes.txt
+++ b/soc/mediatek/mt8192/dpm_release_notes.txt
@@ -1,2 +1,34 @@
-=============== dpm release 2020-08=============
-1. support DRAM suspend and DDR DVFS switch
+** Build from MTK Internal **
+
+# 2020-11-05
+1. Add 4266Mbps suspend/resume support.
+
+# 2020-08-01
+1. Add DRAM suspend/DVFS support.
+
+==============================================================================
+DPM Introduction
+
+ DPM is hardware module which is used for Dram Power Management, which
+is used for dram low power.
+ For example: self refresh, disable PLL/DLL when not used.
+
+ DPM includes two parts of images: data part(dpm.dm) and program part(dpm.pm).
+They are loaded into DPM SRAM when system inits.
+
+1 Who use it?
+ Coreboot will load dpm when mainboard init. It will copy dpm.dm & dpm.pm
+to DPM SRAM.
+
+2 How to load DPM?
+ Use CBFS to load "dpm.dm" and "dpm.pm".
+ No need to pass other parameters to DPM.
+
+3 Return Value?
+ 0 : means load successful;
+ < 0: means load failed.
+ -1: means load dm failed;
+ -2: means load pm failed.
+
+4 Version?
+ No version now.
diff --git a/soc/mediatek/mt8192/dram.elf b/soc/mediatek/mt8192/dram.elf
index 684963b..2918846 100644
--- a/soc/mediatek/mt8192/dram.elf
+++ b/soc/mediatek/mt8192/dram.elf
Binary files differ
diff --git a/soc/mediatek/mt8192/dram_release_notes.txt b/soc/mediatek/mt8192/dram_release_notes.txt
index 290511c..3b981df 100644
--- a/soc/mediatek/mt8192/dram_release_notes.txt
+++ b/soc/mediatek/mt8192/dram_release_notes.txt
@@ -1,4 +1,94 @@
-# 2020.9.16
+# 2020-11-05
-Force dram 4266Mbps.
+1. Built from Chrome OS 13473.0.2020_09_16_2253, incompatible with previous versions.
+ Header version = 4.
+2. Include changes:
+CL:*3398084 dramc: MT8192: add max freq flag
+
+# 2020-09-16
+
+1. Built from Chrome OS 13473.0.2020_09_16_2253.
+2. Include changes:
+
+eed9075 dramc: MT8192: Use clear data rate log format
+c57d520 dramc: MT8192: Adjust vcore voltage to correct value for DDR calibration
+a3651f6 pmic: MT6359: Allow to modify VGPU11 voltage
+bdff3f3 dramc: MT8192: Update the output message for easy debug
+824f1e0 dramc: MT8192: Load correct emi setting by the ddr geometry
+f488694 dramc: MT8192: Save the dramc params result after calibration
+adab87d dramc: MT8192: Update the dramc param struct
+3a1c53e dramc: MT8192: Update the dram control drivers
+a87ece6 dramc: MT8192: Add RX gating fast calibration flow
+c112bf9 dramc: MT8192: Add DRAM full calibration blob source code
+
+===============================================================================
+DRAM Introduction
+
+ Dram.elf is one ELF format file which is used for calibration.
+The dram.elf is loaded by the first time bootup, it will do dram
+full calibration, and save dram parameters to NAND(or EMMC) for
+bootup faster after the first bootup.
+
+1 Who use it?
+ Coreboot loads dram.elf at the first time bootup if no dram
+parameters exist.
+
+2 How to load dram.elf?
+ Coreboot locates dram.elf file, and locate the entry point "_start",
+then it passes dram struct "param", and call _start(¶m) to execute dram.elf
+flow.
+
+3 Parameters
+ struct dramc_param {
+ struct dramc_param_header header; // see below
+ void (*do_putc)(unsigned char c);
+ struct dramc_data dramc_datas; // see below
+ };
+
+ Below shows the internal structure of dramc_param:
+ struct dramc_param_header {
+ u32 checksum; /* checksum of dramc_datas, update in the coreboot */
+ u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */
+ u16 size; /* size of whole dramc_param, update in the coreboot */
+ u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */
+ u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */
+ };
+
+ struct dramc_data {
+ struct ddr_base_info ddr_info;
+ struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
+ };
+
+ struct ddr_base_info {
+ u16 config_dvfs; /* DRAMC_PARAM_DVFS_FLAG */
+ u16 ddr_type; /* DRAMC_PARAM_DDR_TYPE */
+ u16 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */
+ u16 voltage_type; /* DRAM_PARAM_VOLTAGE_TYPE */
+ u32 support_ranks;
+ u64 rank_size[RANK_MAX];
+ struct emi_mdl emi_config;
+ dram_cbt_mode cbt_mode[RANK_MAX];
+ };
+
+ struct sdram_params {
+ u32 rank_num;
+ u16 num_dlycell_perT;
+ u16 delay_cell_timex100;
+
+ /* duty */
+ s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+ s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+ s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+
+ .......
+ .......
+ };
+
+4 The output of dram.elf
+ dram.elf will set the suitable dramc settings, also save the dram parameters
+to NAND(or EMMC) on the specified section: "RW_DDR_TRAINING".
+
+5 Return Values
+ 0 : means successful;
+ < 0: means failed.