UPSTREAM: soc/mediatek/mt8183: Update DRAM calibration blob to 1.5.0
A new release of dram.elf built from Chrome OS 12573.224.0, which
contains the version number string.
BUG=b:173653085
TEST=emerge-kukui coreboot
TEST=Krane boots
BRANCH=kukui
Change-Id: Ic113a6346cb57186efad77e36cc99ec957765b0e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/blobs/+/2816384
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
diff --git a/soc/mediatek/mt8183/README.md b/soc/mediatek/mt8183/README.md
new file mode 100644
index 0000000..f217387
--- /dev/null
+++ b/soc/mediatek/mt8183/README.md
@@ -0,0 +1,111 @@
+# Firmware list
+
+- drame.elf
+
+# `dram.elf` Introduction
+
+`dram.elf` is one ELF format file which is used for calibration.
+The `dram.elf` is loaded at the first bootup. It will do DRAM
+full calibration, and save calibration parameters to NAND/NOR (or EMMC)
+for faster bootup after the first bootup.
+
+## Who uses it
+
+Coreboot loads `dram.elf` at the first time bootup if no DRAM parameters have
+been cached.
+
+
+## How to load `dram.elf`
+
+Coreboot locates `dram.elf` file, and locates the entry point `_start`,
+then it passes DRAM struct `param`, and calls `_start(¶m)` to execute
+`dram.elf` flow.
+
+## Parameters
+
+```
+struct dramc_param {
+ struct dramc_param_header header; // see below
+ void (*do_putc)(unsigned char c);
+ struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; // see below
+};
+```
+
+Below shows the internal structure of `dramc_param`:
+
+```
+struct dramc_param_header {
+ u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */
+ u32 magic; /* DRAMC_PARAM_HEADER_MAGIC */
+ u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */
+ u16 size; /* size of whole dramc_param, update in the coreboot */
+I u16 config; /* DRAMC_PARAM_CONFIG, used for blob */
+ u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */
+ u32 checksum; /* checksum of dramc_datas, update in the coreboot */
+};
+
+struct sdram_params {
+ u16 source;
+ u16 frequency; /* DRAM frequency */
+ u8 rank_num; /* DRAM rank number */
+ u16 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */
+ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+
+ /* DUTY */
+ s8 duty_clk_delay[CHANNEL_MAX];
+ s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+
+ /* CBT */
+ u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER];
+
+ /* Gating */
+ u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+ u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+ u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+ u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+
+ /* TX perbit */
+ u8 tx_vref[CHANNEL_MAX][RANK_MAX];
+ u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+ u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+ u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+ u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+ u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+
+ /* datlat */
+ u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
+
+ /* RX perbit */
+ u8 rx_vref[CHANNEL_MAX];
+ s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+ u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+
+ u32 emi_cona_val;
+ u32 emi_conh_val;
+ u32 emi_conf_val;
+ u32 chn_emi_cona_val[CHANNEL_MAX];
+ u32 cbt_mode_extern;
+ u32 delay_cell_unit;
+};
+```
+
+## Output of `dram.elf`
+
+`dram.elf` will set suitable dramc settings, and save the DRAM parameters
+to NAND/NOR (or EMMC) in the specified section: `RW_DDR_TRAINING`.
+
+## Return Values
+
+- 0 : means successful.
+- < 0 : means failed.
+
+## Version
+
+```
+$ strings dram.elf | grep "firmware version"
+MediaTek DRAM firmware version: 1.5.0
+```
diff --git a/soc/mediatek/mt8183/dram.elf b/soc/mediatek/mt8183/dram.elf
index 644ee65..2ff792e 100644
--- a/soc/mediatek/mt8183/dram.elf
+++ b/soc/mediatek/mt8183/dram.elf
Binary files differ
diff --git a/soc/mediatek/mt8183/dram.elf.md5 b/soc/mediatek/mt8183/dram.elf.md5
index 8e9fe21..b15b705 100644
--- a/soc/mediatek/mt8183/dram.elf.md5
+++ b/soc/mediatek/mt8183/dram.elf.md5
@@ -1 +1 @@
-a47d4e7b78e409afa1a8daa826f3b1b9 *dram.elf
+c2261728217c9e3ca21cb511724dde5d *dram.elf
diff --git a/soc/mediatek/mt8183/dram_release_notes.txt b/soc/mediatek/mt8183/dram_release_notes.txt
index e0a327c..29149b9 100644
--- a/soc/mediatek/mt8183/dram_release_notes.txt
+++ b/soc/mediatek/mt8183/dram_release_notes.txt
@@ -1,3 +1,12 @@
+# 2021.04.06
+1. Build from Chrome OS 12573.224.0, compatible with previous versions.
+ Header version = 5.
+
+2. Include changes:
+
+CL:*3724354 dramc: Do not print if serial console is disabled
+CL:*3724353 dramc: mt8183: Add blob version
+
# 2021.01.20
1. Build from Chrome OS 12573.197.0, incompatible with previous versions.
Header version = 5.