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davidhendricks@gmail.comffdc0932012-02-27 23:46:44 +00001/* Copyright 2012, Google Inc.
2 * All rights reserved.
dhendrix@google.com7d320d22011-02-08 22:21:06 +00003 *
davidhendricks@gmail.comffdc0932012-02-27 23:46:44 +00004 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met:
dhendrix@google.com7d320d22011-02-08 22:21:06 +00007 *
davidhendricks@gmail.comffdc0932012-02-27 23:46:44 +00008 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above
11 * copyright notice, this list of conditions and the following
12 * disclaimer in the documentation and/or other materials provided
13 * with the distribution.
14 * * Neither the name of Google Inc. nor the names of its
15 * contributors may be used to endorse or promote products derived
16 * from this software without specific prior written permission.
dhendrix@google.com7d320d22011-02-08 22:21:06 +000017 *
davidhendricks@gmail.comffdc0932012-02-27 23:46:44 +000018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
dhendrix@google.com7d320d22011-02-08 22:21:06 +000029 *
30 * DDR3 field access for DDR3 SPDs.
31 */
32
33#include <ctype.h>
34#include <stdint.h>
35#include <stdlib.h>
36#include <stdio.h>
37#include <string.h>
38
39#include "mosys/platform.h"
40#include "mosys/kv_pair.h"
David Hendricks7d51ea82014-04-01 17:22:58 -070041#include "mosys/log.h"
dhendrix@google.com7d320d22011-02-08 22:21:06 +000042
43#include "lib/string.h"
dhendrix@google.com7d320d22011-02-08 22:21:06 +000044
45#include "lib/ddr3.h"
dhendrix@google.com7d320d22011-02-08 22:21:06 +000046#include "lib/spd.h"
Jack Rosenthaldf9917b2020-10-21 10:57:39 -060047#include "lib/val2str.h"
dhendrix@google.com7d320d22011-02-08 22:21:06 +000048
dhendrix@google.com1f8bd822011-02-08 22:57:20 +000049#include "jedec_id.h"
50
dhendrix@google.com7d320d22011-02-08 22:21:06 +000051/*
52 * spd_print_field_ddr3 - add common DDR SPD fields into key=value pair
53 *
54 * @intf: platform interface
55 * @kv: key=value pair
56 * @data: raw spd data
57 * @type: type of field to retrieve
58 *
59 * returns 1 to indicate data added to key=value pair
60 * returns 0 to indicate no data added
61 * returns <0 to indicate error
62 *
63 */
64int spd_print_field_ddr3(struct platform_intf *intf, struct kv_pair *kv,
65 const void *data, enum spd_field_type type)
66{
67 int ret;
68 const uint8_t *byte = data;
69
70 ret = 0;
71 switch (type) {
dhendrix@google.com1b1f1d12011-02-12 00:01:04 +000072 case SPD_GET_DRAM_TYPE:
Duncan Laurie8f9820a2016-02-08 14:45:55 -080073 kv_pair_add(kv, "dram",
74 (byte[DDR3_SPD_REG_DEVICE_TYPE] ==
75 SPD_DRAM_TYPE_LPDDR3) ? "LPDDR3" : "DDR3");
dhendrix@google.com1b1f1d12011-02-12 00:01:04 +000076 ret = 1;
77 break;
78 case SPD_GET_MODULE_TYPE:
dhendrix@google.com597d3032011-02-12 00:05:53 +000079 kv_pair_add(kv, "module",
dhendrix@google.com1b1f1d12011-02-12 00:01:04 +000080 val2str(byte[DDR3_SPD_REG_MODULE_TYPE],
81 ddr3_module_type_lut));
82 ret = 1;
83 break;
dhendrix@google.com7d320d22011-02-08 22:21:06 +000084 case SPD_GET_MFG_ID:
85 {
86 uint8_t manuf_lsb;
87 uint8_t manuf_msb;
88 const char *tstr;
89
90 manuf_lsb = byte[DDR3_SPD_REG_MODULE_MANUF_JEDEC_ID_LSB] & 0x7f;
dhendrix@google.com2f6879c2011-02-09 04:29:50 +000091 manuf_msb = byte[DDR3_SPD_REG_MODULE_MANUF_JEDEC_ID_MSB] & 0x7f;
dhendrix@google.com7d320d22011-02-08 22:21:06 +000092
93 tstr = jedec_manufacturer(manuf_lsb, manuf_msb);
94
95 if (tstr != NULL) {
dhendrix@google.com00d74fc2011-02-09 03:02:11 +000096 kv_pair_fmt(kv, "module_mfg", "%u-%u: %s", manuf_lsb + 1,
dhendrix@google.com7d320d22011-02-08 22:21:06 +000097 manuf_msb, tstr);
98 } else {
dhendrix@google.com00d74fc2011-02-09 03:02:11 +000099 kv_pair_fmt(kv, "module_mfg", "%u-%u", manuf_lsb + 1,
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000100 manuf_msb);
101 }
102 ret = 1;
103 break;
104 }
105
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000106 case SPD_GET_PART_NUMBER:
107 {
108 char part[19];
109
110 memcpy(part, &byte[DDR3_SPD_REG_MODULE_PART_NUM_0], 18);
111 part[18] = '\0';
112 kv_pair_fmt(kv, "part_number", "%s", part);
113
114 ret = 1;
115 break;
116 }
117
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000118 case SPD_GET_SIZE:
119 {
120 /* See "Calculating Module Capacity" section in DDR3 SPD
121 * specification for details. */
David Hendricksae2d5422012-07-18 14:52:41 -0700122 unsigned int size;
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000123
124 /* calculate the total size in MB */
125 size = 256 << (byte[DDR3_SPD_REG_DENSITY_BANKS] & 0xf);
126 size >>= 3; /* in terms of bytes instead of bits. */
127 size *= 8 << (byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] & 0x7);
128 size /= 4 << (byte[DDR3_SPD_REG_MODULE_ORG] & 0x7);
129 size *= 1 + ((byte[DDR3_SPD_REG_MODULE_ORG] >> 3) & 0x7);
130
David Hendricksae2d5422012-07-18 14:52:41 -0700131 kv_pair_fmt(kv, "size_mb", "%u", size);
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000132 ret = 1;
133 break;
134 }
135
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000136 case SPD_GET_RANKS:
137 {
138 kv_pair_fmt(kv, "ranks", "%d",
139 1 + ((byte[DDR3_SPD_REG_MODULE_ORG] >> 3) & 0x7));
140 ret = 1;
141 break;
142 }
143
144 case SPD_GET_WIDTH:
145 {
146 /* Total width including ECC. */
147 uint8_t width;
148 width = 8 << (byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] & 0x7);
149 width += 8 * ((byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] >> 3) & 0x7);
150 kv_pair_fmt(kv, "width", "%d", width);
151 ret = 1;
152 break;
153 }
154
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000155 default:
156 {
157 ret = 0; /* force "we don't handle this here */
158 break;
159 }
160 }
161
162 return ret;
163}