davidhendricks@gmail.com | ffdc093 | 2012-02-27 23:46:44 +0000 | [diff] [blame] | 1 | /* Copyright 2012, Google Inc. |
| 2 | * All rights reserved. |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 3 | * |
davidhendricks@gmail.com | ffdc093 | 2012-02-27 23:46:44 +0000 | [diff] [blame] | 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 7 | * |
davidhendricks@gmail.com | ffdc093 | 2012-02-27 23:46:44 +0000 | [diff] [blame] | 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above |
| 11 | * copyright notice, this list of conditions and the following |
| 12 | * disclaimer in the documentation and/or other materials provided |
| 13 | * with the distribution. |
| 14 | * * Neither the name of Google Inc. nor the names of its |
| 15 | * contributors may be used to endorse or promote products derived |
| 16 | * from this software without specific prior written permission. |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 17 | * |
davidhendricks@gmail.com | ffdc093 | 2012-02-27 23:46:44 +0000 | [diff] [blame] | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 19 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 20 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 21 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 22 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 23 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 24 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 25 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 26 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 29 | * |
| 30 | * DDR3 field access for DDR3 SPDs. |
| 31 | */ |
| 32 | |
| 33 | #include <ctype.h> |
| 34 | #include <stdint.h> |
| 35 | #include <stdlib.h> |
| 36 | #include <stdio.h> |
| 37 | #include <string.h> |
| 38 | |
dhendrix@google.com | cc628f5 | 2011-09-28 01:20:37 +0000 | [diff] [blame] | 39 | #include <valstr.h> |
| 40 | |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 41 | #include "mosys/platform.h" |
| 42 | #include "mosys/kv_pair.h" |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 43 | #include "mosys/log.h" |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 44 | |
| 45 | #include "lib/string.h" |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 46 | |
| 47 | #include "lib/ddr3.h" |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 48 | #include "lib/spd.h" |
| 49 | |
dhendrix@google.com | 1f8bd82 | 2011-02-08 22:57:20 +0000 | [diff] [blame] | 50 | #include "jedec_id.h" |
| 51 | |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 52 | /* |
| 53 | * spd_print_field_ddr3 - add common DDR SPD fields into key=value pair |
| 54 | * |
| 55 | * @intf: platform interface |
| 56 | * @kv: key=value pair |
| 57 | * @data: raw spd data |
| 58 | * @type: type of field to retrieve |
| 59 | * |
| 60 | * returns 1 to indicate data added to key=value pair |
| 61 | * returns 0 to indicate no data added |
| 62 | * returns <0 to indicate error |
| 63 | * |
| 64 | */ |
| 65 | int spd_print_field_ddr3(struct platform_intf *intf, struct kv_pair *kv, |
| 66 | const void *data, enum spd_field_type type) |
| 67 | { |
| 68 | int ret; |
| 69 | const uint8_t *byte = data; |
| 70 | |
| 71 | ret = 0; |
| 72 | switch (type) { |
dhendrix@google.com | 1b1f1d1 | 2011-02-12 00:01:04 +0000 | [diff] [blame] | 73 | case SPD_GET_DRAM_TYPE: |
dhendrix@google.com | 597d303 | 2011-02-12 00:05:53 +0000 | [diff] [blame] | 74 | kv_pair_add(kv, "dram", "DDR3"); |
dhendrix@google.com | 1b1f1d1 | 2011-02-12 00:01:04 +0000 | [diff] [blame] | 75 | ret = 1; |
| 76 | break; |
| 77 | case SPD_GET_MODULE_TYPE: |
dhendrix@google.com | 597d303 | 2011-02-12 00:05:53 +0000 | [diff] [blame] | 78 | kv_pair_add(kv, "module", |
dhendrix@google.com | 1b1f1d1 | 2011-02-12 00:01:04 +0000 | [diff] [blame] | 79 | val2str(byte[DDR3_SPD_REG_MODULE_TYPE], |
| 80 | ddr3_module_type_lut)); |
| 81 | ret = 1; |
| 82 | break; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 83 | case SPD_GET_MFG_ID: |
| 84 | { |
| 85 | uint8_t manuf_lsb; |
| 86 | uint8_t manuf_msb; |
| 87 | const char *tstr; |
| 88 | |
| 89 | manuf_lsb = byte[DDR3_SPD_REG_MODULE_MANUF_JEDEC_ID_LSB] & 0x7f; |
dhendrix@google.com | 2f6879c | 2011-02-09 04:29:50 +0000 | [diff] [blame] | 90 | manuf_msb = byte[DDR3_SPD_REG_MODULE_MANUF_JEDEC_ID_MSB] & 0x7f; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 91 | |
| 92 | tstr = jedec_manufacturer(manuf_lsb, manuf_msb); |
| 93 | |
| 94 | if (tstr != NULL) { |
dhendrix@google.com | 00d74fc | 2011-02-09 03:02:11 +0000 | [diff] [blame] | 95 | kv_pair_fmt(kv, "module_mfg", "%u-%u: %s", manuf_lsb + 1, |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 96 | manuf_msb, tstr); |
| 97 | } else { |
dhendrix@google.com | 00d74fc | 2011-02-09 03:02:11 +0000 | [diff] [blame] | 98 | kv_pair_fmt(kv, "module_mfg", "%u-%u", manuf_lsb + 1, |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 99 | manuf_msb); |
| 100 | } |
| 101 | ret = 1; |
| 102 | break; |
| 103 | } |
| 104 | |
| 105 | case SPD_GET_MFG_ID_DRAM: |
| 106 | { |
| 107 | uint8_t manuf_lsb; |
| 108 | uint8_t manuf_msb; |
| 109 | const char *tstr; |
| 110 | |
| 111 | manuf_lsb = byte[DDR3_SPD_REG_DRAM_MANUF_JEDEC_ID_LSB] & 0x7f; |
dhendrix@google.com | 2f6879c | 2011-02-09 04:29:50 +0000 | [diff] [blame] | 112 | manuf_msb = byte[DDR3_SPD_REG_DRAM_MANUF_JEDEC_ID_MSB] & 0x7f; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 113 | |
| 114 | tstr = jedec_manufacturer(manuf_lsb, manuf_msb); |
| 115 | |
| 116 | if (tstr != NULL) { |
dhendrix@google.com | 00d74fc | 2011-02-09 03:02:11 +0000 | [diff] [blame] | 117 | kv_pair_fmt(kv, "dram_mfg", "%u-%u: %s", |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 118 | manuf_lsb + 1, manuf_msb, tstr); |
| 119 | } else { |
dhendrix@google.com | 00d74fc | 2011-02-09 03:02:11 +0000 | [diff] [blame] | 120 | kv_pair_fmt(kv, "dram_mfg", "%u-%u", |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 121 | manuf_lsb + 1, manuf_msb); |
| 122 | } |
| 123 | ret = 1; |
| 124 | break; |
| 125 | } |
| 126 | |
| 127 | case SPD_GET_MFG_LOC: |
| 128 | { |
| 129 | kv_pair_fmt(kv, "mfg_loc", "0x%02x", |
| 130 | byte[DDR3_SPD_REG_MODULE_MANUF_LOC]); |
| 131 | ret = 1; |
| 132 | break; |
| 133 | } |
| 134 | |
| 135 | case SPD_GET_MFG_DATE: /* manufacturing date (BCD values) */ |
| 136 | { |
| 137 | uint8_t year; |
| 138 | uint8_t week; |
| 139 | |
| 140 | year = byte[DDR3_SPD_REG_MODULE_MANUF_DATE_YEAR]; |
| 141 | week = byte[DDR3_SPD_REG_MODULE_MANUF_DATE_YEAR]; |
| 142 | kv_pair_fmt(kv, "mfg_date", "20%02x-wk%02x", week, year); |
| 143 | ret = 1; |
| 144 | break; |
| 145 | } |
| 146 | |
| 147 | case SPD_GET_SERIAL_NUMBER: |
| 148 | { |
dhendrix@google.com | dac5b42 | 2011-02-09 02:43:16 +0000 | [diff] [blame] | 149 | kv_pair_fmt(kv, "serial_number", "%02x%02x%02x%02x", |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 150 | byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_0], |
| 151 | byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_1], |
| 152 | byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_2], |
| 153 | byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_3]); |
| 154 | ret = 1; |
| 155 | break; |
| 156 | } |
| 157 | |
| 158 | case SPD_GET_PART_NUMBER: |
| 159 | { |
| 160 | char part[19]; |
| 161 | |
| 162 | memcpy(part, &byte[DDR3_SPD_REG_MODULE_PART_NUM_0], 18); |
| 163 | part[18] = '\0'; |
| 164 | kv_pair_fmt(kv, "part_number", "%s", part); |
| 165 | |
| 166 | ret = 1; |
| 167 | break; |
| 168 | } |
| 169 | |
| 170 | case SPD_GET_REVISION_CODE: |
| 171 | { |
| 172 | kv_pair_fmt(kv, "revision_code", "0x%02x%02x", |
| 173 | byte[DDR3_SPD_REG_MODULE_REVISION_0], |
| 174 | byte[DDR3_SPD_REG_MODULE_REVISION_1]); |
| 175 | ret = 1; |
| 176 | break; |
| 177 | } |
| 178 | |
| 179 | case SPD_GET_SIZE: |
| 180 | { |
| 181 | /* See "Calculating Module Capacity" section in DDR3 SPD |
| 182 | * specification for details. */ |
David Hendricks | ae2d542 | 2012-07-18 14:52:41 -0700 | [diff] [blame] | 183 | unsigned int size; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 184 | |
| 185 | /* calculate the total size in MB */ |
| 186 | size = 256 << (byte[DDR3_SPD_REG_DENSITY_BANKS] & 0xf); |
| 187 | size >>= 3; /* in terms of bytes instead of bits. */ |
| 188 | size *= 8 << (byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] & 0x7); |
| 189 | size /= 4 << (byte[DDR3_SPD_REG_MODULE_ORG] & 0x7); |
| 190 | size *= 1 + ((byte[DDR3_SPD_REG_MODULE_ORG] >> 3) & 0x7); |
| 191 | |
David Hendricks | ae2d542 | 2012-07-18 14:52:41 -0700 | [diff] [blame] | 192 | kv_pair_fmt(kv, "size_mb", "%u", size); |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 193 | ret = 1; |
| 194 | break; |
| 195 | } |
| 196 | |
| 197 | case SPD_GET_ECC: |
| 198 | { |
| 199 | uint8_t bus_ext_width = byte[DDR3_SPD_REG_MODULE_BUS_WIDTH]; |
| 200 | bus_ext_width >>= 3; |
| 201 | bus_ext_width &= 0x7; |
| 202 | kv_pair_add_bool(kv, "ecc", bus_ext_width); |
| 203 | ret = 1; |
| 204 | break; |
| 205 | } |
| 206 | |
| 207 | case SPD_GET_RANKS: |
| 208 | { |
| 209 | kv_pair_fmt(kv, "ranks", "%d", |
| 210 | 1 + ((byte[DDR3_SPD_REG_MODULE_ORG] >> 3) & 0x7)); |
| 211 | ret = 1; |
| 212 | break; |
| 213 | } |
| 214 | |
| 215 | case SPD_GET_WIDTH: |
| 216 | { |
| 217 | /* Total width including ECC. */ |
| 218 | uint8_t width; |
| 219 | width = 8 << (byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] & 0x7); |
| 220 | width += 8 * ((byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] >> 3) & 0x7); |
| 221 | kv_pair_fmt(kv, "width", "%d", width); |
| 222 | ret = 1; |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | case SPD_GET_CHECKSUM: |
| 227 | { |
| 228 | kv_pair_fmt(kv, "checksum", "0x%02x%02x", |
| 229 | byte[DDR3_SPD_REG_CRC_1], |
| 230 | byte[DDR3_SPD_REG_CRC_0]); |
| 231 | ret = 1; |
| 232 | break; |
| 233 | } |
| 234 | |
| 235 | case SPD_GET_SPEEDS: |
| 236 | { |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 237 | int i, mhz, first_entry; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 238 | char speeds[128]; |
| 239 | const struct valstr possible_mhz[] = { |
David Hendricks | 4f5033a | 2013-04-03 14:10:19 -0700 | [diff] [blame] | 240 | { 400, "DDR3-800" }, |
| 241 | { 533, "DDR3-1066" }, |
| 242 | { 667, "DDR3-1333" }, |
| 243 | { 800, "DDR3-1600" }, |
| 244 | { 933, "DDR3-1866" }, |
| 245 | { 1067, "DDR3-2133" }, |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 246 | { 0 } |
| 247 | }; |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 248 | int tck_mtb = byte[DDR3_SPD_REG_TCK_MIN]; |
| 249 | int mtb_dividend = byte[DDR3_SPD_REG_MTB_DIVIDEND]; |
| 250 | int mtb_divisor = byte[DDR3_SPD_REG_MTB_DIVISOR]; |
| 251 | int ftb_dividend = byte[DDR3_SPD_REG_FTB_DIVIDEND_DIVSOR] >> 4; |
| 252 | int ftb_divisor = byte[DDR3_SPD_REG_FTB_DIVIDEND_DIVSOR] & 0xf; |
| 253 | double tck_ns, mtb = 0.0, ftb_ns = 0.0; |
| 254 | /* fine offset is encoded in 2's complement format */ |
| 255 | int8_t ftb_offset = byte[DDR3_SPD_REG_FINE_OFFSET_TCK_MIN]; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 256 | |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 257 | /* Sanity check that MTB and FTB values are >=1 (as per spec) */ |
| 258 | ret = -1; |
| 259 | if (!mtb_dividend) |
| 260 | lprintf(LOG_ERR, "Invalid MTB dividend from SPD\n"); |
| 261 | else if (!mtb_divisor) |
| 262 | lprintf(LOG_ERR, "Invalid MTB divisor from SPD\n"); |
| 263 | else if (!ftb_dividend) |
| 264 | lprintf(LOG_ERR, "Invalid FTB dividend from SPD\n"); |
| 265 | else if (!ftb_divisor) |
| 266 | lprintf(LOG_ERR, "Invalid FTB divisor from SPD\n"); |
| 267 | else |
| 268 | ret = 0; |
| 269 | if (ret) |
| 270 | break; |
| 271 | |
| 272 | mtb = (double)mtb_dividend / mtb_divisor; |
| 273 | ftb_ns = ((double)(ftb_dividend) / ftb_divisor) / 1000; |
| 274 | tck_ns = tck_mtb * mtb + (ftb_offset * ftb_ns); |
| 275 | mhz = (int)((double)1000/tck_ns); |
| 276 | |
| 277 | lprintf(LOG_DEBUG, "%s: %d * %.03fns + %d * %.03fns = %.02fns," |
| 278 | " mhz = %d\n", __func__, |
| 279 | tck_mtb, mtb, ftb_offset, ftb_ns, tck_ns, mhz); |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 280 | |
| 281 | memset(speeds, 0, sizeof(speeds)); |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 282 | first_entry = 1; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 283 | for (i = 0; possible_mhz[i].val != 0; i++) { |
dhendrix@google.com | 04cdd4f | 2011-09-21 22:20:32 +0000 | [diff] [blame] | 284 | double min = possible_mhz[i].val * 0.99; |
| 285 | |
| 286 | if (min <= mhz) { |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 287 | if (!first_entry) |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 288 | strcat(speeds, ", "); |
David Hendricks | 7d51ea8 | 2014-04-01 17:22:58 -0700 | [diff] [blame] | 289 | first_entry = 0; |
dhendrix@google.com | 7d320d2 | 2011-02-08 22:21:06 +0000 | [diff] [blame] | 290 | strcat(speeds, possible_mhz[i].str); |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | kv_pair_add(kv, "speeds", speeds); |
| 295 | ret = 1; |
| 296 | break; |
| 297 | } |
| 298 | |
| 299 | default: |
| 300 | { |
| 301 | ret = 0; /* force "we don't handle this here */ |
| 302 | break; |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | return ret; |
| 307 | } |