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gerrit.openfyde.cn / chromium.googlesource.com / chromiumos / platform / mosys / 6638f8709a2892cd760f7ad5bc06cb30feea949d / . / lib / spd / nonspd_modules.c
blob: b42bb3cc29cd1a03c86940854cc567d65cec268a [file] [log] [blame]
David Hendricks6638f872015-11-04 14:52:02 -0800[diff] [blame^]1/*
2 * Copyright 2015, Google Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
15 * * Neither the name of Google Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "lib/nonspd.h"
33
34const struct nonspd_mem_info elpida_8gbit_lpddr3_edfa164a2ma_jd_f = {
35 .dram_type = SPD_DRAM_TYPE_LPDDR3,
36 .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
37
38 .module_size_mbits = 8192,
39 .num_ranks = 2,
40 .device_width = 32,
41 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800, DDR_933 },
42
43 .module_mfg_id = { .msb = 0x2c, .lsb = 0x80 },
44 .dram_mfg_id = { .msb = 0x2c, .lsb = 0x80 },
45
46 .part_num =
47 { 'E', 'D', 'F', 'A', '1', '6', '4', 'A', '2', 'M', 'A', '-',
48 'J', 'D', '-', 'F',},
49};
50
51const struct nonspd_mem_info elpida_8gbit_lpddr3_f8132a3ma_gd_f = {
52 .dram_type = SPD_DRAM_TYPE_LPDDR3,
53 .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
54
55 .module_size_mbits = 8192,
56 .num_ranks = 2,
57 .device_width = 32,
58 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
59
60 .module_mfg_id = { .msb = 0x2c, .lsb = 0x80 },
61 .dram_mfg_id = { .msb = 0x2c, .lsb = 0x80 },
62
63 .part_num =
64 { 'F', '8', '1', '3', '2', 'A', '3', 'M', 'A', '-', 'G', 'D',
65 '-', 'F',},
66};
67
68const struct nonspd_mem_info elpida_16gbit_lpddr3_fa232a2ma_gc_f = {
69 .dram_type = SPD_DRAM_TYPE_LPDDR3,
70 .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
71
72 .module_size_mbits = 16384,
73 .num_ranks = 2,
74 .device_width = 32,
75 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
76
77 .module_mfg_id = { .msb = 0x2c, .lsb = 0x80 },
78 .dram_mfg_id = { .msb = 0x2c, .lsb = 0x80 },
79
80 .part_num =
81 { 'F', 'A', '2', '3', '2', 'A', '2', 'M', 'A', '-', 'G', 'C',
82 '-', 'F',},
83};
84
85const struct nonspd_mem_info hynix_4gbit_ddr3l_h5tc4g63afr_pba = {
86 .dram_type = SPD_DRAM_TYPE_DDR3,
87 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
88
89 .module_size_mbits = 4096,
90 .num_ranks = 1,
91 .device_width = 16,
92 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
93
94 .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
95 .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
96
97 .serial_num = { 0, 0, 0, 0 },
98 .part_num =
99 { 'H', '5', 'T', 'C', '4', 'G', '6', '3', 'A', 'F', 'R', '-',
100 'P', 'B', 'A'},
101};
102
103const struct nonspd_mem_info hynix_4gbit_ddr3l_h5tc4g63cfr_pba = {
104 .dram_type = SPD_DRAM_TYPE_DDR3,
105 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
106
107 .module_size_mbits = 4096,
108 .num_ranks = 1,
109 .device_width = 16,
110 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
111
112 .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
113 .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
114
115 .serial_num = { 0, 0, 0, 0 },
116 .part_num =
117 { 'H', '5', 'T', 'C', '4', 'G', '6', '3', 'C', 'F', 'R', '-',
118 'P', 'B', 'A'},
119};
120
121const struct nonspd_mem_info hynix_2gbit_lpddr3_h9ccnnn8gtmlar_nud = {
122 .dram_type = SPD_DRAM_TYPE_LPDDR3,
123 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
124
125 .module_size_mbits = 8192,
126 .num_ranks = 1,
127 .device_width = 32,
128 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
129
130 .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
131 .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
132
133 .part_num =
134 { 'H', '9', 'C', 'C', 'N', 'N', 'N', '8', 'G', 'T', 'M', 'L',
135 'A', 'R', '-', 'N', 'U', 'D',},
136};
137
138const struct nonspd_mem_info hynix_4gbit_lpddr3_h9ccnnnbjtmlar_nud = {
139 .dram_type = SPD_DRAM_TYPE_LPDDR3,
140 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
141
142 .module_size_mbits = 16384,
143 .num_ranks = 2,
144 .device_width = 32,
145 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
146
147 .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
148 .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
149
150 .part_num =
151 { 'H', '9', 'C', 'C', 'N', 'N', 'N', 'B', 'J', 'T', 'M', 'L',
152 'A', 'R', '-', 'N', 'U', 'D',},
153};
154
155const struct nonspd_mem_info hynix_8gbit_ddr3l_h5tc8g63amr_pba = {
156 .dram_type = SPD_DRAM_TYPE_DDR3,
157 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
158 .module_size_mbits = 8192,
159 .num_ranks = 2,
160 .device_width = 16,
161 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
162
163 .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
164 .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
165
166 .serial_num = { 0, 0, 0, 0 },
167 .part_num =
168 { 'H', '5', 'T', 'C', '8', 'G', '6', '3', 'A', 'M', 'R', '-',
169 'P', 'B', 'A' },
170};
171
172const struct nonspd_mem_info hynix_8gbit_lpddr3_h9ccnnn8gtmlar_nud = {
173 .dram_type = SPD_DRAM_TYPE_LPDDR3,
174 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
175
176 .module_size_mbits = 16384,
177 .num_ranks = 1,
178 .device_width = 32,
179 .ddr_freq = { DDR_533, DDR_667, DDR_800 },
180
181 .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
182 .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
183
184 .part_num =
185 { 'H', '9', 'C', 'C', 'N', 'N', 'N', '8', 'G', 'T', 'M', 'L',
186 'A', 'R', '-', 'N', 'U', 'D',},
187};
188
189const struct nonspd_mem_info micron_mt41k256m16ha = {
190 .dram_type = SPD_DRAM_TYPE_DDR3,
191 .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
192
193 .module_size_mbits = 4096,
194 .num_ranks = 1,
195 .device_width = 16,
196 .ddr_freq = { DDR_533, DDR_667, DDR_800 },
197
198 .module_mfg_id = { .msb = 0x2c, .lsb = 0x00 },
199 .dram_mfg_id = { .msb = 0x2c, .lsb = 0x00 },
200
201 .serial_num = { 0, 0, 0, 0 },
202 .part_num = { 'M', 'T', '4', '1', 'K', '2', '5', '6', 'M',
203 '1', '6', 'H', 'A', '-', '1', '2', '5' },
204};
205
206const struct nonspd_mem_info samsung_k4b4g1646d = {
207 .dram_type = SPD_DRAM_TYPE_DDR3,
208 .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
209
210 .module_size_mbits = 4096,
211 .num_ranks = 1,
212 .device_width = 16,
213 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800 },
214
215 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
216 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
217
218 .serial_num = { 0, 0, 0, 0 },
219 .part_num =
220 { 'K', '4', 'B', '4', 'G', '1', '6', '4', '6', 'D',
221 '-', 'B', 'Y', 'K', '0' },
222};
223
224const struct nonspd_mem_info samsung_k4b4g1646e = {
225 .dram_type = SPD_DRAM_TYPE_DDR3,
226 .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
227
228 .module_size_mbits = 4096,
229 .num_ranks = 1,
230 .device_width = 16,
231 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800 },
232
233 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
234 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
235
236 .serial_num = { 0, 0, 0, 0 },
237 .part_num =
238 { 'K', '4', 'B', '4', 'G', '1', '6', '4', '6', 'E',
239 '-', 'B', 'Y', 'K', '0' },
240};
241
242const struct nonspd_mem_info samsung_4gbit_ddr3l_k4b4g1646d_byk0 = {
243 .dram_type = SPD_DRAM_TYPE_DDR3,
244 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
245
246 .module_size_mbits = 4096,
247 .num_ranks = 1,
248 .device_width = 16,
249 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800 },
250
251 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
252 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
253
254 .serial_num = { 0, 0, 0, 0 },
255 .part_num =
256 { 'K', '4', 'B', '4', 'G', '1', '6', '4', '6', 'D', '-',
257 'B', 'Y', 'K', '0' },
258};
259
260const struct nonspd_mem_info samsung_4gbit_ddr3l_k4b4g1646q_hyk0 = {
261 .dram_type = SPD_DRAM_TYPE_DDR3,
262 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
263
264 .module_size_mbits = 4096,
265 .num_ranks = 1,
266 .device_width = 16,
267 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800 },
268
269 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
270 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
271
272 .serial_num = { 0, 0, 0, 0 },
273 .part_num =
274 { 'K', '4', 'B', '4', 'G', '1', '6', '4', '6', 'Q', '-',
275 'H', 'Y', 'K', '0' },
276};
277
278const struct nonspd_mem_info samsung_8gbit_ddr3l_k4b8g1646q_myk0 = {
279 .dram_type = SPD_DRAM_TYPE_DDR3,
280 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
281 .module_size_mbits = 8192,
282 .num_ranks = 2,
283 .device_width = 16,
284 .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
285
286 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
287 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
288
289 .serial_num = { 0, 0, 0, 0 },
290 .part_num =
291 { 'K', '4', 'B', '8', 'G', '1', '6', '4', '6', 'Q', '-',
292 'M', 'Y', 'K', '0' },
293};
294
295const struct nonspd_mem_info samsung_2gbit_lpddr3_k3qf2f20em_agce = {
296 .dram_type = SPD_DRAM_TYPE_LPDDR3,
297 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
298
299 .module_size_mbits = 8192,
300 .num_ranks = 2,
301 .device_width = 32,
302 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800 },
303
304 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
305 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
306
307 .part_num =
308 { 'K', '3', 'Q', 'F', '2', 'F', '2', '0', 'E', 'M', '-',
309 'A', 'G', 'C', 'E' },
310};
311
312const struct nonspd_mem_info samsung_4gbit_lpddr3_k4e6e304ee_egce = {
313 .dram_type = SPD_DRAM_TYPE_LPDDR3,
314 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
315
316 .module_size_mbits = 16384,
317 .num_ranks = 2,
318 .device_width = 32,
319 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800, DDR_933},
320
321 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
322 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
323
324 .part_num =
325 { 'K', '4', 'E', '6', 'E', '3', '0', '4', 'E', 'E', '-',
326 'E', 'G', 'C', 'E' },
327};
328
329const struct nonspd_mem_info samsung_8gbit_lpddr3_k4e8e304ed_egcc = {
330 .dram_type = SPD_DRAM_TYPE_DDR3,
331 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
332
333 .module_size_mbits = 8192,
334 .num_ranks = 2,
335 .device_width = 32,
336 .ddr_freq = { DDR_533 },
337
338 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
339 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
340
341 .serial_num = { 0, 0, 0, 0 },
342 .part_num =
343 { 'K', '4', 'E', '8', 'E', '3', '0', '4', 'E', 'D', '-',
344 'E', 'G', 'C', 'C' },
345};
346
347const struct nonspd_mem_info samsung_2gbit_lpddr3_k4e8e304ee_egce = {
348 .dram_type = SPD_DRAM_TYPE_LPDDR3,
349 .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
350
351 .module_size_mbits = 8192,
352 .num_ranks = 2,
353 .device_width = 32,
354 .ddr_freq = { DDR_400, DDR_533, DDR_667, DDR_800, DDR_933 },
355
356 .module_mfg_id = { .msb = 0xce, .lsb = 0x00 },
357 .dram_mfg_id = { .msb = 0xce, .lsb = 0x00 },
358
359 .part_num =
360 { 'K', '4', 'E', '8', 'E', '3', '0', '4', 'E', 'E', '-',
361 'E', 'G', 'C', 'E' },
362};