blob: 925c0c1b1cbc49e0126099bc635fa75351304d1b [file] [log] [blame]
dhendrix@google.com7d320d22011-02-08 22:21:06 +00001/*
2 * Copyright (C) 2011 Google Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
17 *
18 * DDR3 field access for DDR3 SPDs.
19 */
20
21#include <ctype.h>
22#include <stdint.h>
23#include <stdlib.h>
24#include <stdio.h>
25#include <string.h>
26
27#include "mosys/platform.h"
28#include "mosys/kv_pair.h"
29
30#include "lib/string.h"
31#include "lib/valstr.h"
32
33#include "lib/ddr3.h"
dhendrix@google.com7d320d22011-02-08 22:21:06 +000034#include "lib/spd.h"
35
dhendrix@google.com1f8bd822011-02-08 22:57:20 +000036#include "jedec_id.h"
37
dhendrix@google.com7d320d22011-02-08 22:21:06 +000038/*
39 * spd_print_field_ddr3 - add common DDR SPD fields into key=value pair
40 *
41 * @intf: platform interface
42 * @kv: key=value pair
43 * @data: raw spd data
44 * @type: type of field to retrieve
45 *
46 * returns 1 to indicate data added to key=value pair
47 * returns 0 to indicate no data added
48 * returns <0 to indicate error
49 *
50 */
51int spd_print_field_ddr3(struct platform_intf *intf, struct kv_pair *kv,
52 const void *data, enum spd_field_type type)
53{
54 int ret;
55 const uint8_t *byte = data;
56
57 ret = 0;
58 switch (type) {
59 case SPD_GET_MFG_ID:
60 {
61 uint8_t manuf_lsb;
62 uint8_t manuf_msb;
63 const char *tstr;
64
65 manuf_lsb = byte[DDR3_SPD_REG_MODULE_MANUF_JEDEC_ID_LSB] & 0x7f;
dhendrix@google.com2f6879c2011-02-09 04:29:50 +000066 manuf_msb = byte[DDR3_SPD_REG_MODULE_MANUF_JEDEC_ID_MSB] & 0x7f;
dhendrix@google.com7d320d22011-02-08 22:21:06 +000067
68 tstr = jedec_manufacturer(manuf_lsb, manuf_msb);
69
70 if (tstr != NULL) {
dhendrix@google.com00d74fc2011-02-09 03:02:11 +000071 kv_pair_fmt(kv, "module_mfg", "%u-%u: %s", manuf_lsb + 1,
dhendrix@google.com7d320d22011-02-08 22:21:06 +000072 manuf_msb, tstr);
73 } else {
dhendrix@google.com00d74fc2011-02-09 03:02:11 +000074 kv_pair_fmt(kv, "module_mfg", "%u-%u", manuf_lsb + 1,
dhendrix@google.com7d320d22011-02-08 22:21:06 +000075 manuf_msb);
76 }
77 ret = 1;
78 break;
79 }
80
81 case SPD_GET_MFG_ID_DRAM:
82 {
83 uint8_t manuf_lsb;
84 uint8_t manuf_msb;
85 const char *tstr;
86
87 manuf_lsb = byte[DDR3_SPD_REG_DRAM_MANUF_JEDEC_ID_LSB] & 0x7f;
dhendrix@google.com2f6879c2011-02-09 04:29:50 +000088 manuf_msb = byte[DDR3_SPD_REG_DRAM_MANUF_JEDEC_ID_MSB] & 0x7f;
dhendrix@google.com7d320d22011-02-08 22:21:06 +000089
90 tstr = jedec_manufacturer(manuf_lsb, manuf_msb);
91
92 if (tstr != NULL) {
dhendrix@google.com00d74fc2011-02-09 03:02:11 +000093 kv_pair_fmt(kv, "dram_mfg", "%u-%u: %s",
dhendrix@google.com7d320d22011-02-08 22:21:06 +000094 manuf_lsb + 1, manuf_msb, tstr);
95 } else {
dhendrix@google.com00d74fc2011-02-09 03:02:11 +000096 kv_pair_fmt(kv, "dram_mfg", "%u-%u",
dhendrix@google.com7d320d22011-02-08 22:21:06 +000097 manuf_lsb + 1, manuf_msb);
98 }
99 ret = 1;
100 break;
101 }
102
103 case SPD_GET_MFG_LOC:
104 {
105 kv_pair_fmt(kv, "mfg_loc", "0x%02x",
106 byte[DDR3_SPD_REG_MODULE_MANUF_LOC]);
107 ret = 1;
108 break;
109 }
110
111 case SPD_GET_MFG_DATE: /* manufacturing date (BCD values) */
112 {
113 uint8_t year;
114 uint8_t week;
115
116 year = byte[DDR3_SPD_REG_MODULE_MANUF_DATE_YEAR];
117 week = byte[DDR3_SPD_REG_MODULE_MANUF_DATE_YEAR];
118 kv_pair_fmt(kv, "mfg_date", "20%02x-wk%02x", week, year);
119 ret = 1;
120 break;
121 }
122
123 case SPD_GET_SERIAL_NUMBER:
124 {
dhendrix@google.comdac5b422011-02-09 02:43:16 +0000125 kv_pair_fmt(kv, "serial_number", "%02x%02x%02x%02x",
dhendrix@google.com7d320d22011-02-08 22:21:06 +0000126 byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_0],
127 byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_1],
128 byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_2],
129 byte[DDR3_SPD_REG_MODULE_MANUF_SERIAL_3]);
130 ret = 1;
131 break;
132 }
133
134 case SPD_GET_PART_NUMBER:
135 {
136 char part[19];
137
138 memcpy(part, &byte[DDR3_SPD_REG_MODULE_PART_NUM_0], 18);
139 part[18] = '\0';
140 kv_pair_fmt(kv, "part_number", "%s", part);
141
142 ret = 1;
143 break;
144 }
145
146 case SPD_GET_REVISION_CODE:
147 {
148 kv_pair_fmt(kv, "revision_code", "0x%02x%02x",
149 byte[DDR3_SPD_REG_MODULE_REVISION_0],
150 byte[DDR3_SPD_REG_MODULE_REVISION_1]);
151 ret = 1;
152 break;
153 }
154
155 case SPD_GET_SIZE:
156 {
157 /* See "Calculating Module Capacity" section in DDR3 SPD
158 * specification for details. */
159 long size;
160
161 /* calculate the total size in MB */
162 size = 256 << (byte[DDR3_SPD_REG_DENSITY_BANKS] & 0xf);
163 size >>= 3; /* in terms of bytes instead of bits. */
164 size *= 8 << (byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] & 0x7);
165 size /= 4 << (byte[DDR3_SPD_REG_MODULE_ORG] & 0x7);
166 size *= 1 + ((byte[DDR3_SPD_REG_MODULE_ORG] >> 3) & 0x7);
167
168 kv_pair_fmt(kv, "size", "%llu", size);
169 ret = 1;
170 break;
171 }
172
173 case SPD_GET_ECC:
174 {
175 uint8_t bus_ext_width = byte[DDR3_SPD_REG_MODULE_BUS_WIDTH];
176 bus_ext_width >>= 3;
177 bus_ext_width &= 0x7;
178 kv_pair_add_bool(kv, "ecc", bus_ext_width);
179 ret = 1;
180 break;
181 }
182
183 case SPD_GET_RANKS:
184 {
185 kv_pair_fmt(kv, "ranks", "%d",
186 1 + ((byte[DDR3_SPD_REG_MODULE_ORG] >> 3) & 0x7));
187 ret = 1;
188 break;
189 }
190
191 case SPD_GET_WIDTH:
192 {
193 /* Total width including ECC. */
194 uint8_t width;
195 width = 8 << (byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] & 0x7);
196 width += 8 * ((byte[DDR3_SPD_REG_MODULE_BUS_WIDTH] >> 3) & 0x7);
197 kv_pair_fmt(kv, "width", "%d", width);
198 ret = 1;
199 break;
200 }
201
202 case SPD_GET_CHECKSUM:
203 {
204 kv_pair_fmt(kv, "checksum", "0x%02x%02x",
205 byte[DDR3_SPD_REG_CRC_1],
206 byte[DDR3_SPD_REG_CRC_0]);
207 ret = 1;
208 break;
209 }
210
211 case SPD_GET_SPEEDS:
212 {
213 int i;
214 int mhz;
215 int one_added;
216 char speeds[128];
217 const struct valstr possible_mhz[] = {
218 { 400, "DDR3-800" },
219 { 533, "DDR3-1066" },
220 { 667, "DDR3-1333" },
221 { 800, "DDR3-1600" },
222 { 0 }
223 };
224
225 mhz = 1000 * byte[DDR3_SPD_REG_MTB_DIVISOR];
226 mhz /= byte[DDR3_SPD_REG_MTB_DIVIDEND];
227 mhz /= byte[DDR3_SPD_REG_TCK_MIN];
228
229 memset(speeds, 0, sizeof(speeds));
230 one_added = 0;
231 for (i = 0; possible_mhz[i].val != 0; i++) {
232 if (possible_mhz[i].val <= mhz) {
233 if (one_added) {
234 strcat(speeds, ", ");
235 }
236 one_added = 1;
237 strcat(speeds, possible_mhz[i].str);
238 }
239 }
240
241 kv_pair_add(kv, "speeds", speeds);
242 ret = 1;
243 break;
244 }
245
246 default:
247 {
248 ret = 0; /* force "we don't handle this here */
249 break;
250 }
251 }
252
253 return ret;
254}