CHERRY-PICK: spring: revise DRAM representation
Spring uses two channels, each with 2 512MByte chips with 16 data
lines to each chip.
This patch makes the representation provided by mosys somewhat more
consistent with how the hardware is actually laid out. The chips on
each channel will be represented as a logical DIMM, with a single
bus (16-bits x 2 = 32) and size (512MByte * 2 = 1GByte).
BUG=chrome-os-partner:18934
BRANCH=spring
TEST=manually tested on Spring by forcing each fake SPD to be used.
Example "mosys -k memory spd print geometry" output:
dimm="0" size_mb="1024" ranks="1" width="32"
dimm="1" size_mb="1024" ranks="1" width="32"
Change-Id: I7678b5335ac66aba2cb9f8ee5b953cb196a001a1
Reviewed-on: https://gerrit.chromium.org/gerrit/50890
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51506
diff --git a/platform/experimental/spring/memory.c b/platform/experimental/spring/memory.c
index ab62ad5..9557a56 100644
--- a/platform/experimental/spring/memory.c
+++ b/platform/experimental/spring/memory.c
@@ -37,8 +37,8 @@
#include "spring.h"
-/* we're not using DIMMs, so count it as a single logical "slot" */
-#define SPRING_DIMM_COUNT 1
+/* Each channel will be represented as a logical DIMM */
+#define SPRING_DIMM_COUNT 2
/* Fake SPD data for now (based off Elpida SPD for Snow) */
static const uint8_t fake_spd[SPD_MAX_LENGTH] = {
@@ -46,11 +46,11 @@
[DDR3_SPD_REG_REVISION] = 0x10,
[DDR3_SPD_REG_DEVICE_TYPE] = 0x0b,
[DDR3_SPD_REG_MODULE_TYPE] = 0x03,
- [DDR3_SPD_REG_DENSITY_BANKS] = 0x03, /* 8 banks * 256MB = 2GBytes */
+ [DDR3_SPD_REG_DENSITY_BANKS] = 0x04, /* 8 banks * 512Mbits = 4Gb */
[DDR3_SPD_REG_ADDRESSING] = 0x32, /* 15 rows, 10 cols */
[DDR3_SPD_REG_VOLTAGE] = 0x02, /* 1.35V */
- [DDR3_SPD_REG_MODULE_ORG] = 0x01, /* 1 rank, x8 */
- [DDR3_SPD_REG_MODULE_BUS_WIDTH] = 0x03,
+ [DDR3_SPD_REG_MODULE_ORG] = 0x02, /* 1 rank, x16 */
+ [DDR3_SPD_REG_MODULE_BUS_WIDTH] = 0x02, /* 32-bits */
/* DDR3-1666 = (1/8)ns * 10 = 1.25ns */
[DDR3_SPD_REG_MTB_DIVIDEND] = 1,
@@ -100,11 +100,11 @@
[DDR3_SPD_REG_REVISION] = 0x12,
[DDR3_SPD_REG_DEVICE_TYPE] = 0x0b,
[DDR3_SPD_REG_MODULE_TYPE] = 0x03,
- [DDR3_SPD_REG_DENSITY_BANKS] = 0x03, /* HACK */
+ [DDR3_SPD_REG_DENSITY_BANKS] = 0x04, /* 8 banks * 512Mbits = 4Gb */
[DDR3_SPD_REG_ADDRESSING] = 0x32, /* 15 rows, 10 cols */
[DDR3_SPD_REG_VOLTAGE] = 0x02, /* 1.35V */
- [DDR3_SPD_REG_MODULE_ORG] = 0x01, /* 1 rank, x8 */
- [DDR3_SPD_REG_MODULE_BUS_WIDTH] = 0x03,
+ [DDR3_SPD_REG_MODULE_ORG] = 0x02, /* 1 rank, x16 */
+ [DDR3_SPD_REG_MODULE_BUS_WIDTH] = 0x02, /* 32-bits */
/* DDR3-1600 = (1/8)ns * 10 = 1.25ns */
[DDR3_SPD_REG_MTB_DIVIDEND] = 1,
@@ -155,11 +155,11 @@
[DDR3_SPD_REG_REVISION] = 0x12,
[DDR3_SPD_REG_DEVICE_TYPE] = 0x0b,
[DDR3_SPD_REG_MODULE_TYPE] = 0x03,
- [DDR3_SPD_REG_DENSITY_BANKS] = 0x03, /* HACK */
+ [DDR3_SPD_REG_DENSITY_BANKS] = 0x04, /* 8 banks * 512Mbits = 4Gb */
[DDR3_SPD_REG_ADDRESSING] = 0x32, /* 15 rows, 10 cols */
[DDR3_SPD_REG_VOLTAGE] = 0x02, /* 1.35V */
- [DDR3_SPD_REG_MODULE_ORG] = 0x01, /* 1 rank, x8 */
- [DDR3_SPD_REG_MODULE_BUS_WIDTH] = 0x03,
+ [DDR3_SPD_REG_MODULE_ORG] = 0x02, /* 1 rank, x16 */
+ [DDR3_SPD_REG_MODULE_BUS_WIDTH] = 0x02, /* 32-bits */
/* DDR3-1600 = (1/8)ns * 10 = 1.25ns */
[DDR3_SPD_REG_MTB_DIVIDEND] = 1,