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Stéphane Marchesin25a26062014-09-12 16:18:59 -07001/*
2 * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_ROCKCHIP
Stéphane Marchesin25a26062014-09-12 16:18:59 -07008
Zach Reizner58080df2016-04-27 11:14:41 -07009#include <assert.h>
10#include <errno.h>
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070011#include <stdio.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070012#include <string.h>
13#include <xf86drm.h>
14#include <rockchip_drm.h>
15
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070016#include "drv_priv.h"
Dominik Behre13ac282015-01-13 00:59:21 -080017#include "helpers.h"
Zach Reizner58080df2016-04-27 11:14:41 -070018#include "util.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070019
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070020static int drv_rockchip_bo_create(struct bo *bo,
Stéphane Marchesined475b42016-02-26 13:36:22 -080021 uint32_t width, uint32_t height,
22 uint32_t format, uint32_t flags)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070023{
Zach Reizner58080df2016-04-27 11:14:41 -070024 size_t plane;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070025
Zach Reizner58080df2016-04-27 11:14:41 -070026 switch (format) {
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070027 case DRV_FORMAT_NV12:
Gurchetan Singhf64487b2016-07-14 19:54:44 -070028 width = ALIGN(width, 4);
29 height = ALIGN(height, 4);
30 bo->strides[0] = bo->strides[1] = width;
31 bo->sizes[0] = height * bo->strides[0];
32 bo->sizes[1] = height * bo->strides[1] / 2;
33 bo->offsets[0] = 0;
34 bo->offsets[1] = height * bo->strides[0];
35 break;
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070036 case DRV_FORMAT_XRGB8888:
37 case DRV_FORMAT_ARGB8888:
38 case DRV_FORMAT_ABGR8888:
39 bo->strides[0] = drv_stride_from_format(format, width);
Gurchetan Singhf64487b2016-07-14 19:54:44 -070040 bo->sizes[0] = height * bo->strides[0];
41 bo->offsets[0] = 0;
42 break;
43 default:
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070044 fprintf(stderr, "drv: rockchip: unsupported format %4.4s\n",
Gurchetan Singhf64487b2016-07-14 19:54:44 -070045 (char*)&format);
46 assert(0);
47 return -EINVAL;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070048 }
Stéphane Marchesin25a26062014-09-12 16:18:59 -070049
Zach Reizner58080df2016-04-27 11:14:41 -070050 int ret;
Gurchetan Singhf64487b2016-07-14 19:54:44 -070051 size_t size = 0;
Zach Reizner58080df2016-04-27 11:14:41 -070052
Gurchetan Singhf64487b2016-07-14 19:54:44 -070053 for (plane = 0; plane < bo->num_planes; plane++)
54 size += bo->sizes[plane];
Zach Reizner58080df2016-04-27 11:14:41 -070055
Gurchetan Singhf64487b2016-07-14 19:54:44 -070056 struct drm_rockchip_gem_create gem_create;
Zach Reizner58080df2016-04-27 11:14:41 -070057
Gurchetan Singhf64487b2016-07-14 19:54:44 -070058 memset(&gem_create, 0, sizeof(gem_create));
59 gem_create.size = size;
60
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070061 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_ROCKCHIP_GEM_CREATE,
Gurchetan Singhf64487b2016-07-14 19:54:44 -070062 &gem_create);
63
64 if (ret) {
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070065 fprintf(stderr, "drv: DRM_IOCTL_ROCKCHIP_GEM_CREATE failed "
Gurchetan Singhf64487b2016-07-14 19:54:44 -070066 "(size=%zu)\n", size);
Zach Reizner58080df2016-04-27 11:14:41 -070067 }
Gurchetan Singhf64487b2016-07-14 19:54:44 -070068 else {
69 for (plane = 0; plane < bo->num_planes; plane++)
70 bo->handles[plane].u32 = gem_create.handle;
Zach Reizner58080df2016-04-27 11:14:41 -070071 }
72
73 return ret;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070074}
75
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070076const struct backend backend_rockchip =
Stéphane Marchesin25a26062014-09-12 16:18:59 -070077{
78 .name = "rockchip",
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070079 .bo_create = drv_rockchip_bo_create,
80 .bo_destroy = drv_gem_bo_destroy,
Stéphane Marchesin25a26062014-09-12 16:18:59 -070081 .format_list = {
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070082 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING},
83 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR},
84 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING},
85 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR},
86 {DRV_FORMAT_ABGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING},
87 {DRV_FORMAT_NV12, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
88 {DRV_FORMAT_NV12, DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR},
Stéphane Marchesin25a26062014-09-12 16:18:59 -070089 }
90};
91
92#endif