commit cf55e3b368158e0ecfa83d1e53f7659ce1d0c33a
author David Lattimore <dml@google.com> Tue Feb 01 12:07:30 2022 +1100
committer Commit Bot <commit-bot@chromium.org> Wed Feb 09 06:08:35 2022 +0000
tree 7563f8dc6eb29789328bcfd09be387d8410f3b30
parent e52c08fc1b5f3c9bfd34e73e21b96e027b41f399

stage1_app: Don't allow reset_fpga when FPGA isn't running

Although reset_fpga is a dev-only feature, it allowed bypassing the SPI
flash hash check even when the no-hash-check wasn't enabled.

BUG=b:217276076
TEST=./scripts/proto2-run
TEST=TFLM=0 ./scripts/fpga-rom-run

Change-Id: I7042a20e5df06efda9d5b09e3853bb5feefdd2ca
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/hps-firmware/+/3428426
Reviewed-by: Dan Callaghan <dcallagh@chromium.org>
Commit-Queue: David Lattimore <dml@chromium.org>
Tested-by: David Lattimore <dml@chromium.org>

scripts/fpga-rom-run

diff --git a/scripts/fpga-rom-run b/scripts/fpga-rom-run
index 7184cdd..0e5c10f 100755
--- a/scripts/fpga-rom-run
+++ b/scripts/fpga-rom-run
@@ -18,5 +18,5 @@
     --openocd-port 4444 \
     --gateware "${PROJECT_ROOT}/build/hps_platform/gateware/hps_platform.bit" \
     --soc-rom "${ROM}" \
-    --cmd 'reset_mcu; write_gateware; write_soc_rom; reset_fpga' \
+    --cmd 'reset_mcu; write_gateware; write_soc_rom; launch_app_without_i2c' \
     "$@"